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參數(shù)資料
| 型號： | CY7B991V-7JXC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | Low Voltage Programmable Skew Clock Buffer |
| 中文描述： | 7B SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC32 |
| 封裝： | LEAD FREE, PLASTIC, LCC-32 |
| 文件頁數(shù)： | 1/14頁 |
| 文件大?。?/td> | 293K |
| 代理商： | CY7B991V-7JXC |
Low Voltage Programmable Skew Clock Buffer
CY7B991V
3.3V RoboClock
Cypress Semiconductor Corporation
Document Number: 38-07141 Rev. *C
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised June 20, 2007
Features
■
All output pair skew <100 ps typical (250 max)
■
3.75 to 80 MHz output operation
■
User selectable output functions
Selectable skew to 18 ns
Inverted and non-inverted
Operation at
1
2
and
1
4
input frequency
Operation at 2x and 4x input frequency (input as low as 3.75
MHz)
■
Zero input to output delay
■
50% duty cycle outputs
■
LVTTL outputs drive 50
Ω
terminated lines
■
Operates from a single 3.3V supply
■
Low operating current
■
32-pin PLCC package
■
Jitter 100 ps (typical)
Functional Description
The CY7B991V Low voltage Programmable Skew Clock Buffer
(LVPSCB) offers user selectable control over system clock
functions. These multiple output clock drivers provide the system
integrator with functions necessary to optimize the timing of
high-performance computer systems. Each of the eight
individual drivers, arranged in four pairs of user controllable
outputs can drive terminated transmission lines with impedances
as low as 50
Ω
. This delivers minimal and specified output skews and
full swing logic levels (LVTTL).
Each output is hardwired to one of nine delay or function config-
urations. Delay increments of 0.7 to 1.5 ns are determined by the
operating frequency with outputs able to skew up to ±6 time units
from their nominal “zero” skew position. The completely
integrated PLL allows external load and transmission line delay
effects to be canceled. When this “zero delay” capability of the
LVPSCB is combined with the selectable output skew functions,
the user can create output-to-output delays of up to ±12 time
units.
Divide-by-two and divide-by-four output functions are provided
for additional flexibility in designing complex clock systems.
When combined with the internal PLL, these divide functions
enable distribution of a low frequency clock that is multiplied by
two or four at the clock destination. This facility minimizes clock
distribution difficulty allowing maximum system clock speed and
flexibility.
TEST
FB
REF
VCO AND
TIME UNIT
GENERATOR
FS
SELECT
INPUTS
(THREE
LEVEL)
SKEW
SELECT
MATRIX
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
FILTER
PHASE
FREQ
DET
Logic Block Diagram
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7B991V-7JXCT | Low Voltage Programmable Skew Clock Buffer |
| CY7C006V | 3.3V 16K x 8 Dual-Port Static RAM(3.3V 16Kx 8 位雙端口靜態(tài)RAM) |
| CY7C1016V | 3.3V 16Kx9 Dual-Port Static RAM(3.3V 16Kx 9 位雙端口靜態(tài)RAM) |
| CY7C138V | 3.3V 4Kx 8 Dual-Port Static RAM(3.3V 4Kx 8 位雙端口靜態(tài)RAM) |
| CY7C139V | 3.3V 4Kx9 Dual-Port Static RAM(3.3V 4Kx 9 位雙端口靜態(tài)RAM) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7B991V-7JXCT | 功能描述:鎖相環(huán) - PLL 3.3V 80MHz 8 TTL COM Programable RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY7B992 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Programmable Skew Clock Buffer |
| CY7B992.2JC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Programmable Skew Clock Buffer |
| CY7B992.2JCT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Programmable Skew Clock Buffer |
| CY7B992.5JC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Programmable Skew Clock Buffer |
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