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參數(shù)資料
| 型號(hào)： | CY7B9911-7JC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | Programmable Skew Clock Buffer (PSCB) |
| 中文描述： | 7B SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC32 |
| 封裝： | PLASTIC, LCC-32 |
| 文件頁(yè)數(shù)： | 1/12頁(yè) |
| 文件大小： | 249K |
| 代理商： | CY7B9911-7JC |
Programmable Skew Clock Buffer (PSCB)
CY7B9911
RoboClock+
Cypress Semiconductor Corporation
Document #: 38-07209 Rev. **
3901 North First Street
San Jose
CA 95134
Revised September 26, 2001
408-943-2600
lock+
Features
All output pair skew <100 ps typical (250 max.)
3.75- to 100-MHz output operation
User-selectable output functions
—Selectable skew to 18 ns
—Inverted and non-inverted
—Operation at and input frequency
—Operation at 2x and 4x input frequency (input as low
as 3.75 MHz)
Zero input to output delay
50% duty-cycle outputs
Outputs drive 50
terminated lines
Low operating current
32-pin PLCC/LCC package
Jitter < 200 ps peak-to-peak (< 25 ps RMS)
Compatible with a Pentium
-based processor
Functional Description
The CY7B9911 High Speed Programmable Skew Clock Buffer
(PSCB) offers user-selectable control over system clock func-
tions. This multiple-output clock driver provides the system in-
tegrator with functions necessary to optimize the timing of
high-performance computer systems. Eight individual TTL
drivers, arranged as four pairs of user-controllable outputs,
can each drive terminated transmission lines with impedances
as low as 50
while delivering minimal and specified output skews
and full-swing logic levels.
Each output can be hardwired to one of nine delay or function
configurations. Delay increments of 0.6 to 1.5 ns are deter-
mined by the operating frequency with outputs able to skew up
to
±
6 time units from their nominal
“
zero
”
skew position. The com-
pletely integrated PLL allows external load and transmission line
delay effects to be canceled. When this
“
zero delay
”
capability of the
PSCB is combined with the selectable output skew functions, the
user can create output-to-output delays of up to
±
12 time units.
Divide-by-two and divide-by-four output functions are provided
for additional flexibility in designing complex clock systems.
When combined with the internal PLL, these divide functions
allow distribution of a low-frequency clock that can be multi-
plied by two or four at the clock destination. This facility mini-
mizes clock distribution difficulty while allowing maximum sys-
tem clock speed and flexibility.
Pentium is a trademark of Intel Corporation.
Logic Block Diagram
Pin Configuration
7B9911
–
1
7B9911
–
2
TEST
FB
REF
VCO AND
TIME UNIT
GENERATOR
FS
SELECT
INPUTS
(THREE
LEVEL)
SKEW
SELECT
MATRIX
1
2
3
4
32
31 30
17
16
15
14
18 19
20
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
3
F
V
R
G
T
2
F
2
2
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
C
2F0
GND
1F1
1F0
V
CCN
1Q0
1Q1
GND
GND
3
3
C
V
C
V
3F1
4F0
4F1
V
CCQ
V
CCN
4Q1
4Q0
GND
GND
PLCC/LCC
CY7B9911
FILTER
PHASE
FREQ
DET
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7B9911V-5JCT | High Speed Low Voltage Programmable Skew Clock Buffer |
| CY7B9911V-5JXC | High Speed Low Voltage Programmable Skew Clock Buffer |
| CY7B9911V-5JXCT | High Speed Low Voltage Programmable Skew Clock Buffer |
| CY7B9911V-7JCT | High Speed Low Voltage Programmable Skew Clock Buffer |
| CY7B9911V-7JXC | High Speed Low Voltage Programmable Skew Clock Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7B9911V | 制造商:Cypress Semiconductor 功能描述: |
| CY7B9911V_07 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:High Speed Low Voltage Programmable Skew Clock Buffer |
| CY7B9911V_11 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:High Speed Low Voltage Programmable Skew Clock Buffer |
| CY7B9911V5JC | 制造商:Cypress Semiconductor 功能描述: |
| CY7B9911V-5JC | 功能描述:鎖相環(huán) - PLL 3.3V 110MHz 8 TTL Programable COM RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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