參數(shù)資料
型號(hào)： CY7B991-2JC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類(lèi)： 時(shí)鐘及定時(shí)
英文描述： Programmable Skew Clock Buffer
中文描述： 7B SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC32
封裝： PLASTIC, LCC-32
文件頁(yè)數(shù)： 1/15頁(yè)
文件大?。?/td> 288K
代理商： CY7B991-2JC
Programmable Skew Clock Buffer
CY7B991
CY7B992
Cypress Semiconductor Corporation
Document #: 38-07138 Rev. **
3901 North First Street
San Jose
CA 95134
Revised September 26, 2001
408-943-2600
92
Features
All output pair skew <100 ps typical (250 max.)
3.75- to 80-MHz output operation
User-selectable output functions
—Selectable skew to 18 ns
—Inverted and non-inverted
—Operation at
1
2
and
1
4
input frequency
—Operation at 2x and 4x input frequency (input as low
as 3.75 MHz)
Zero input to output delay
50% duty-cycle outputs
Outputs drive 50
terminated lines
Low operating current
32-pin PLCC/LCC package
Jitter < 200 ps peak-to-peak (< 25 ps RMS)
Compatible with a Pentium
-based processor
Functional Description
The CY7B991 and CY7B992 Programmable Skew Clock Buff-
ers (PSCB) offer user-selectable control over system clock
functions. These multiple-output clock drivers provide the sys-
tem integrator with functions necessary to optimize the timing
of high-performance computer systems. Eight individual driv-
ers, arranged as four pairs of user-controllable outputs, can
each drive terminated transmission lines with impedances as
low as 50
while delivering minimal and specified output skews
and full-swing logic levels (CY7B991 TTL or CY7B992 CMOS).
Each output can be hardwired to one of nine delay or function
configurations. Delay increments of 0.7 to 1.5 ns are deter-
mined by the operating frequency with outputs able to skew up
to
±
6 time units from their nominal
“
zero
”
skew position. The com-
pletely integrated PLL allows external load and transmission line
delay effects to be canceled. When this
“
zero delay
”
capability of the
PSCB is combined with the selectable output skew functions, the
user can create output-to-output delays of up to
±
12 time units.
Divide-by-two and divide-by-four output functions are provided
for additional flexibility in designing complex clock systems.
When combined with the internal PLL, these divide functions
allow distribution of a low-frequency clock that can be multi-
plied by two or four at the clock destination. This facility mini-
mizes clock distribution difficulty while allowing maximum sys-
tem clock speed and flexibility.
Pentium is a trademark of Intel Corporation.
Logic Block Diagram
Pin Configuration
7B991
–
1
7B991
–
2
TEST
FB
REF
VCO AND
TIME UNIT
GENERATOR
FS
SELECT
INPUTS
(THREE
LEVEL)
SKEW
SELECT
MATRIX
1
2
3
4
32
31 30
17
16
15
14
18 19
20
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
3
F
V
R
G
T
2
F
2
2
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
C
2F0
GND
1F1
1F0
V
CCN
1Q0
1Q1
GND
GND
3
3
C
V
C
V
3F1
4F0
4F1
V
CCQ
V
CCN
4Q1
4Q0
GND
GND
PLCC/LCC
CY7B991
CY7B992
FILTER
PHASE
FREQ
DET
相關(guān)PDF資料
PDF描述
CY7B991-5 Programmable Skew Clock Buffer
CY7B991-5JC Programmable Skew Clock Buffer
CY7B991-5JI Programmable Skew Clock Buffer
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CY7B991 Programmable Skew Clock Buffer
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CY7B9912V 制造商:Cypress Semiconductor 功能描述:
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