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參數(shù)資料
| 型號： | CY62167EV30LL-45ZXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 16-Mbit (1M x 16 / 2M x 8) Static RAM |
| 中文描述： | 1M X 16 STANDARD SRAM, 45 ns, PDSO48 |
| 封裝： | 12 X 18.40 MM, 1 MM HEIGHT, LEAD FREE, MO-142, TSOP1-48 |
| 文件頁數(shù)： | 1/13頁 |
| 文件大?。?/td> | 427K |
| 代理商： | CY62167EV30LL-45ZXI |
Cypress Semiconductor Corporation
Document #: 38-05446 Rev. *C
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised June 04, 2007
CY62167EV30 MoBL
16-Mbit (1M x 16 / 2M x 8) Static RAM
Features
TSOP I package configurable as 1M x 16 or as 2M x 8 SRAM
Very high speed: 45 ns
Wide voltage range: 2.20V–3.60V
Ultra low standby power
— Typical standby current: 1.5
μ
A
— Maximum standby current: 12
μ
A
Ultra low active power
— Typical active current: 2.2 mA @ f = 1 MHz
Easy memory expansion with CE
1
, CE
2
, and OE features
Automatic power down when deselected
CMOS for optimum speed/power
Offered in Pb-free 48-ball BGA and 48-pin TSOP I packages
Functional Description
[1]
The CY62167EV30 is a high performance CMOS static RAM
organized as 1M words by 16 bits / 2M words by 8 bits. This
device features advanced circuit design to provide an ultra low
active current. This is ideal for providing More Battery Life
(MoBL
) in portable applications such as cellular telephones.
The device also has an automatic power down feature that
significantly reduces power consumption by 99% when
addresses are not toggling. Place the device into standby
mode when deselected (CE
1
HIGH or CE
2
LOW or both BHE
and BLE are HIGH). The input and output pins (IO
0
through
IO
15
) are placed in a high-impedance state when: the device
is deselected (CE
1
HIGH or CE
2
LOW), outputs are disabled
(OE HIGH), both Byte High Enable and Byte Low Enable are
disabled (BHE, BLE HIGH), or a write operation is in progress
(CE
1
LOW, CE
2
HIGH and WE LOW).
To write to the device, take Chip Enables (CE
1
LOW and CE
2
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable
(BLE) is LOW, then data from IO pins (IO
0
through IO
7
) is
written into the location specified on the address pins (A
0
through A
19
). If Byte High Enable (BHE) is LOW, then data
from the IO pins (IO
8
through IO
15
) is written into the location
specified on the address pins (A
0
through A
19
).
To read from the device, take Chip Enables (CE
1
LOW and
CE
2
HIGH) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on IO
0
to IO
7
. If Byte High Enable (BHE) is
LOW, then data from memory will appear on IO
8
to IO
15
. See
the
“Truth Table” on page 10
for a complete description of read
and write modes.
Logic Block Diagram
1M × 16 / 2M x 8
RAM Array
IO
0
–IO
7
R
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
COLUMN DECODER
A
1
A
1
A
1
A
1
A
1
S
DATA IN DRIVERS
OE
IO
8
–IO
15
WE
BLE
BHE
A
1
A
0
A
1
A
9
A
1
A
10
CE
2
CE
1
A
1
BYTE
Power Down
Circuit
BHE
BLE
CE
2
CE
1
Note
1. For best practice recommendations, refer to the Cypress application note
AN1064, SRAM System Guidelines
.
[+] Feedback
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| CY62167EV30LL-45ZXI | 制造商:Cypress Semiconductor 功能描述:IC SRAM 16MBIT PARALLEL 45NS TSOP-48 |
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