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參數(shù)資料
| 型號(hào)： | CY62158EV30LL-45BVXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類(lèi)： | DRAM |
| 英文描述： | 8-Mbit (1024K x 8) Static RAM |
| 中文描述： | 1M X 8 STANDARD SRAM, 45 ns, PBGA48 |
| 封裝： | 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48 |
| 文件頁(yè)數(shù)： | 1/11頁(yè) |
| 文件大小： | 921K |
| 代理商： | CY62158EV30LL-45BVXI |
8-Mbit (1024K x 8) Static RAM
CY62158EV30 MoBL
Cypress Semiconductor Corporation
Document #: 38-05578 Rev. *D
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised April 19, 2007
Features
Very high speed: 45 ns
— Wide voltage range:
2.20V–3.60V
Pin compatible with CY62158DV30
Ultra low standby power
— Typical standby current: 2
μ
A
— Maximum standby current: 8
μ
A
Ultra low active power
— Typical active current: 1.8 mA @ f = 1 MHz
Easy memory expansion with CE
1
, CE
2
, and OE features
Automatic power down when deselected
CMOS for optimum speed/power
Offered in Pb-free 48-ball VFBGA, 44-pin TSOP II and
48-pin TSOP I packages
[1]
Functional Description
[2]
The CY62158EV30 is a high performance CMOS static RAM
organized as 1024K words by 8 bits. This device features
advanced circuit design to provide ultra low active current.
This is ideal for providing More Battery Life (MoBL
) in
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
reduces power consumption. Placing the device into standby
mode reduces power consumption significantly when
deselected (CE
1
HIGH or CE
2
LOW). The eight input and
output pins (IO
0
through IO
7
) are placed in a high impedance
state when the device is deselected (CE
1
HIGH or CE
2
LOW),
the outputs are disabled (OE HIGH), or a write operation is in
progress (CE
1
LOW and CE
2
HIGH and WE LOW).
To write to the device, take Chip Enables (CE
1
LOW and CE
2
HIGH) and Write Enable (WE) input LOW. Data on the eight
IO pins (IO
0
through IO
7
) is then written into the location
specified on the address pins (A
0
through A
19
).
To read from the device, take Chip Enables (CE
1
LOW and
CE
2
HIGH) and OE LOW while forcing the WE HIGH. Under
these conditions, the contents of the memory location
specified by the address pins appear on the IO pins. See the
“Truth Table” on page 8
for a complete description of read and
write modes.
Logic Block Diagram
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
IO0
IO7
IO1
IO2
IO3
IO4
IO5
IO6
S
POWER
DOWN
WE
OE
A
A
A
A
R
COLUMN DECODER
1024K x 8
ARRAY
DATA IN DRIVERS
A
CE1
CE2
A
A
Notes
1. For 48 pin TSOP I pin configuration and ordering information, please refer to CY62157EV30 Data sheet.
2. For best practice recommendations, refer to the Cypress application note
“System Design Guidelines”
at
http://www.cypress.com.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY62158EV30LL-45BVXIT | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 8M ULTRA LO PWR HI SPD 靜態(tài)隨機(jī)存取存儲(chǔ)器 IND RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY62158EV30LL-45IKU | 制造商:Cypress Semiconductor 功能描述: |
| CY62158EV30LL45ZSXI | 制造商:Cypress Semiconductor 功能描述: |
| CY62158EV30LL-45ZSXI | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 8M ULTRA LO PWR HI SPD 靜態(tài)隨機(jī)存取存儲(chǔ)器 IND RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY62158EV30LL-45ZSXI | 制造商:Cypress Semiconductor 功能描述:IC SRAM 8MBIT PARALLEL 45NS TSOP-44 制造商:Cypress Semiconductor 功能描述:IC, SRAM, 8MBIT, PARALLEL, 45NS, TSOP-44 |
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