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參數(shù)資料
| 型號： | CY62128BLL-55ZAXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 128K x 8 Static RAM |
| 中文描述： | 128K X 8 STANDARD SRAM, 55 ns, PDSO32 |
| 封裝： | 8 X 13.40 MM, LEAD FREE, STSOP1-32 |
| 文件頁數(shù)： | 1/11頁 |
| 文件大?。?/td> | 340K |
| 代理商： | CY62128BLL-55ZAXI |
128K x 8 Static RAM
CY62128B
MoBL
Cypress Semiconductor Corporation
Document #: 38-05300 Rev. *C
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised February 14, 2005
Features
Temperature Ranges
— Commercial: 0°C to 70°C
— Industrial: –40°C to 85°C
— Automotive: –40°C to 125°C
4.5V – 5.5V operation
CMOS for optimum speed/power
Low active power
(70 ns, LL version, Commercial, Industrial)
— 82.5 mW (max.) (15 mA)
Low standby power
(70 ns, LL version, Commercial, Industrial)
— 110
μ
W (max.) (15
μ
A)
Automatic power-down when deselected
TTL-compatible inputs and outputs
Easy memory expansion with CE
1
, CE
2
, and OE options
Functional Description
[1]
The CY62128B is a high-performance CMOS static RAM
organized as 131,072 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE
1
),
an active HIGH Chip Enable (CE
2
), an active LOW Output
Enable (OE), and three-state drivers. This device has an
automatic
power-down
feature
consumption by more than 75% when deselected.
Writing to the device is accomplished by taking Chip Enable
One (CE
1
) and Write Enable (WE) inputs LOW and Chip
Enable Two (CE
2
) input HIGH. Data on the eight I/O pins (I/O
0
through I/O
7
) is then written into the location specified on the
address pins (A
0
through A
16
).
Reading from the device is accomplished by taking Chip
Enable One (CE
1
) and Output Enable (OE) LOW while forcing
Write Enable (WE) and Chip Enable Two (CE
2
) HIGH. Under
these conditions, the contents of the memory location
specified by the address pins will appear on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
1
HIGH or CE
2
LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE
1
LOW, CE
2
HIGH, and WE LOW).
The CY62128B is available in a standard 450-mil-wide SOIC,
32-pin TSOP type I and STSOP packages.
that
reduces
power
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
1
A
1
A
Logic Block Diagram
A1
A2
A3
A4
A5
A6
A7
A8
COLUMN
DECODER
R
S
INPUT BUFFER
POWER
DOWN
WE
OE
I/O0
I/O1
I/O2
I/O3
512x256x8
ARRAY
I/O7
I/O6
I/O5
I/O4
A0
A
A
1
A
A
CE2
A
1
A
9
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY62128BLL-55ZC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| CY62128BLL-55ZI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:128K x 8 Static RAM |
| CY62128BLL-55ZRC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| CY62128BLL-55ZRI | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 5V 1M-Bit 128K x 8 55ns 32-Pin RTSOP 制造商:Rochester Electronics LLC 功能描述:1MB (128K X 8)- SLOW ASYNCH SRAM - Bulk |
| CY62128BLL-55ZRIT | 制造商:Rochester Electronics LLC 功能描述:1MB (128K X 8)- SLOW ASYNCH SRAM - Tape and Reel |
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