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參數(shù)資料
| 型號(hào)： | CY54FCT821ATLM |
| 英文描述： | 10-Bit D-Type Flip-Flop |
| 中文描述： | 10位D型觸發(fā)器 |
| 文件頁(yè)數(shù)： | 6/7頁(yè) |
| 文件大小： | 101K |
| 代理商： | CY54FCT821ATLM |
CY54FCT540T, CY74FCT540T
8-BIT BUFFERS/LINE DRIVERS
WITH 3-STATE OUTPUTS
SCCS029A
–
MAY 1994
–
REVISED OCTOBER 2001
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
3 V
3 V
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Data Input
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
3 V
0 V
Input
Out-of-Phase
Output
In-Phase
Output
Timing Input
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Control
Output
Waveform 1
(see Note B)
Output
Waveform 2
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
≈
3.5 V
0 V
VOL
+ 0.3 V
≈
0 V
3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7 V
Open
TEST
S1
3 V
0 V
tw
VOLTAGE WAVEFORMS
PULSE DURATION
Input
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. The outputs are measured one at a time with one input transition per measurement.
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT FOR
3-STATE OUTPUTS
S1
7 V
500
GND
From Output
Under Test
CL = 50 pF
(see Note A)
Test
Point
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
Open
VOH
–
0.3 V
500
500
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
Figure 1. Load Circuit and Voltage Waveforms
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| CY54FCT821BTDM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:10-Bit D-Type Flip-Flop |
| CY54FCT821BTLM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:10-Bit D-Type Flip-Flop |
| CY54FCT821CTDM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:10-Bit D-Type Flip-Flop |
| CY54FCT821CTLM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:10-Bit D-Type Flip-Flop |
| CY54FCT823ATDM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:9-Bit D-Type Flip-Flop |
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