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參數(shù)資料
| 型號： | CY3930V256-200MGC |
| 廠商： | Cypress Semiconductor Corp. |
| 元件分類： | 晶體 |
| 英文描述： | CRYSTAL, HC-49, 12MHZ; Frequency, output:12000kHz; Accuracy:+/-50ppm; Temperature, operating range:-10(degree C) to +70(degree C); Capacitance, load:12pF; Crystal case type:HC49U-S; Series:HC49SFWB; Temperature stabilty:+/-50ppm; RoHS Compliant: Yes |
| 中文描述： | CPLD器件在FPGA的密度 |
| 文件頁數(shù)： | 40/86頁 |
| 文件大?。?/td> | 1212K |
| 代理商： | CY3930V256-200MGC |
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Delta39K ISR
CPLD Family
Document #: 38-03039 Rev. *H
Page 40 of 86
CPLD Boot EEPROM
[17]
Part Numbers (Ordering Information)
Recommended ATMEL CPLD Boot EEPROM for corresponding Delta39K CPLDs
Note:
17. Refer to the data sheets at www.atmel.com for detailed architectural and timing information.
39K200
181
CY39200V208-181NTC
CY39200V484-181BBC
CY39200V388-181MGC
CY39200V676-181MBC
CY39200V208-125NTC
CY39200V484-125BBC
CY39200V388-125MGC
CY39200V676-125MBC
CY39200V208-125NTI
CY39200V484-125BBI
CY39200V208-83NTC
CY39200V484-83BBC
CY39200V388-83MGC
CY39200V676-83MBC
CY39200V208-83NTI
CY39200V484-83BBI
NT208
BB484
MG388
MB676
NT208
BB484
MG388
MB676
NT208
BB484
NT208
BB484
MG388
MB676
NT208
BB484
208-Lead Enhanced Quad Flat Pack
484-Lead Fine Pitch Ball Grid Array
388-Lead Ball Grid Array
676-Lead Fine Pitch Ball Grid Array
208-Lead Enhanced Quad Flat Pack
484-Lead Fine Pitch Ball Grid Array
388-Lead Ball Grid Array
676-Lead Fine Pitch Ball Grid Array
208-Lead Enhanced Quad Flat Pack
484-Lead Fine Pitch Ball Grid Array
208-Lead Enhanced Quad Flat Pack
484-Lead Fine Pitch Ball Grid Array
388-Lead Ball Grid Array
676-Lead Fine Pitch Ball Grid Array
208-Lead Enhanced Quad Flat Pack
484-Lead Fine Pitch Ball Grid Array
Commercial
÷
÷
125
Commercial
÷
÷
Industrial
83
Commercial
÷
÷
Industrial
Delta39K Part Numbers (Ordering Information)
(continued)
Device
Speed
(MHz)
Ordering Code
Package
Name
Package Type
Self-Boot
Solution
Operating
Range
Device
2 Mbit
Speed
(MHz)
15
10
15
10
15
10
Ordering Code
AT17LV002-10JC
AT17LV002-10JC
AT17LV010-10JC
AT17LV010-10JI
AT17LV512-10JC
AT17LV512-10JI
Package
Name
20J
20J
20J
20J
20J
20J
Package Type
Operating
Range
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
20-Lead Plastic Leaded Chip Carrier
20-Lead Plastic Leaded Chip Carrier
20-Lead Plastic Leaded Chip Carrier
20-Lead Plastic Leaded Chip Carrier
20-Lead Plastic Leaded Chip Carrier
20-Lead Plastic Leaded Chip Carrier
1 Mbit
512 Kbit
CPLD Device
39K30
39K50
39K100
39K165
39K200
Recommended boot EEPROM
AT17LV512
AT17LV512
AT17LV010
AT17LV002
AT17LV002
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY3950V256-200MGC | CPLDs at FPGA Densities |
| CY39100V256-200MGC | CPLDs at FPGA Densities |
| CY39165V256-200MGC | CPLDs at FPGA Densities |
| CY39200V256-200MGC | CPLDs at FPGA Densities |
| CY3930Z256-200MGC | CPLDs at FPGA Densities |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY3930V256-233MGC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY3930V256-233MGI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY3930V256-233NTC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY3930V388-125MGC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY3930V388-181MBC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
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