參數(shù)資料
型號(hào)： CY39200Z256-181MGC
廠(chǎng)商： Cypress Semiconductor Corp.
英文描述： CPLDs at FPGA Densities
中文描述： CPLD器件在FPGA的密度
文件頁(yè)數(shù)： 45/86頁(yè)
文件大?。?/td> 1212K
代理商： CY39200Z256-181MGC
Delta39K ISR
CPLD Family
Document #: 38-03039 Rev. *H
Page 45 of 86
Pin Tables
Package Diagrams
(continued)
676-Ball FBGA (27 x 27 x 1.6 mm) BB676/MB676
51-85125-*B
Table 8. Pin Definition Table
Pin Name
GCLK0-3
GCTL0-3
GND
IO/V
REF0
IO/V
REF1
IO/V
REF2
IO/V
REF3
IO/V
REF4
IO/V
REF5
IO/V
REF6
IO/V
REF7
IO
IO6/Lock
MSEL
Function
Input
Input
Ground
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input
Description
Global Clock signals 0 through 3
Global Control signals 0 through 3
Ground
Dual function pin: IO or Reference Voltage for Bank 0
Dual function pin: IO or Reference Voltage for Bank 1
Dual function pin: IO or Reference Voltage for Bank 2
Dual function pin: IO or Reference Voltage for Bank 3
Dual function pin: IO or Reference Voltage for Bank 4
Dual function pin: IO or Reference Voltage for Bank 5
Dual function pin: IO or Reference Voltage for Bank 6
Dual function pin: IO or Reference Voltage for Bank 7
Input or Output pin
Dual function pin: IO in Bank 6 or PLL lock output signal
Mode Select Pin (see
Table 9
)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY39200Z256-181NC 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39200Z256-233MGC 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39200Z256-233MGI 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39200Z256-233NTC 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39200Z388-125BBC 制造商:CYPRESS 制造商全稱(chēng):Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
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