參數(shù)資料
型號(hào)： CY39165Z676-125MBI
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類(lèi)： PLD
英文描述： CPLDs at FPGA Densities
中文描述： LOADABLE PLD, 10 ns, PBGA676
封裝： 27 X 27 MM, 1.60 MM HEIGHT, 1 MM PITCH, FBGA-676
文件頁(yè)數(shù)： 22/86頁(yè)
文件大?。?/td> 1212K
代理商： CY39165Z676-125MBI
Delta39K ISR
CPLD Family
Document #: 38-03039 Rev. *H
Page 22 of 86
Input and Output Standard Timing Delay
Adjustments
All the timing specifications in this data sheet are specified
based on LVCMOS compliant inputs and outputs (fast slew
rates).
[15]
Apply following adjustments if the inputs and outputs
are configured to operate at other standards.
t
INDUTY
f
PLLO[14]
f
PLLI[14]
f
PLLVCO
P
SAPLLI
f
MPLLI
JTAG Parameters
t
JCKH
t
JCKL
t
JCP
t
JSU
t
JH
t
JCO
t
JXZ
t
JZX
40
6.2
12.5
100
–0.3
60
266
133
266
+0.3
50
40
6.2
12.5
100
–0.3
60
266
133
266
+0.3
50
40
6.2
12.5
100
–0.3
60
266
133
266
+0.3
50
40
6.2
12.5
100
–0.3
60
200
100
266
+0.3
50
40
6.2
12.5
100
–0.3
60
200
100
266
+0.3
50
%
MHz
MHz
MHz
%
KHz
25
25
50
10
10
25
25
50
10
10
25
25
50
10
10
25
25
50
10
10
25
25
50
10
10
ns
ns
ns
ns
ns
ns
ns
ns
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
Switching Characteristics — Parameter Values
Over the Operating Range (continued)
Parameter
233
200
181
125
83
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
I/O Standard
LVTTL – 2 mA
LVTTL – 4 mA
LVTTL – 6 mA
LVTTL – 8 mA
LVTTL – 12 mA
LVTTL – 16 mA
LVTTL – 24 mA
LVCMOS
LVCMOS3
LVCMOS2
LVCMOS18
3.3V PCI
GTL+
SSTL3 I
SSTL3 II
Output Delay Adjustments
Input Delay Adjustments
t
IOIN
t
CKIN
0
0
0
0
0
0
0
0
0.1
0.1
0.2
0.2
0.5
0.4
0
0.5
0.4
0.5
0.3
0.5
0.3
Fast Slew Rate
t
EA
2.75
1.8
1.8
1.2
0.6
0.16
0
0
0.14
0.05
0.41
1.6
–0.14
0.02
[16]
0.6
[16]
–0.15
–0.4
Slow Slew Rate
(additional delay to fast slew rate)
t
IODSLOW
t
EASLOW
2.6
2.0
2.5
2.0
2.5
2.0
2.4
2.0
2.3
2.0
2.0
2.0
1.6
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.1
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
t
IOD
t
ER
t
ERSLOW
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
t
IOREGPIN
0
0
0
0
0
0
0
0
0.2
0.4
0.3
0
0.2
0.3
0.3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0.1
0.7
0
0.1
0
0.9
[16]
0.1
0
0
0.3
0.2
Notes:
14. Refer to page 11 and the application note titled
“Delta39K PLL and Clock Tree”
for details on the PLL operation.
15. For “slow slew rate” output delay adjustments, refer to
Warp
software’s static timing analyzer results.
16. These delays are based on falling edge output. The rising edge delay depends on the size of pull-up resistor and termination voltage.
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