參數(shù)資料
型號: CY39165V676-125MBC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: PLD
英文描述: CPLDs at FPGA Densities
中文描述: LOADABLE PLD, 10 ns, PBGA676
封裝: 27 X 27 MM, 1.6 MM HEIGHT, 1 MM PITCH, FBGA-676
文件頁數(shù): 42/86頁
文件大?。?/td> 1212K
代理商: CY39165V676-125MBC
Delta39K ISR
CPLD Family
Document #: 38-03039 Rev. *H
Page 42 of 86
Package Diagrams
(continued)
388-Lead Ball Grid Array MG388
51-85103-*C
相關(guān)PDF資料
PDF描述
CY39165V676-125MBI CPLDs at FPGA Densities
CY39165V676-125MGC CPLDs at FPGA Densities
CY39165V676-125MGI CPLDs at FPGA Densities
CY39165V676-125NC CPLDs at FPGA Densities
CY39165V676-125NI CPLDs at FPGA Densities
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY39165V676-125MBI 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39165V676-125MGC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39165V676-125MGI 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39165V676-125NC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39165V676-125NI 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities