參數(shù)資料
型號(hào): CY39100Z484-125BBI
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: PLD
英文描述: CPLDs at FPGA Densities
中文描述: LOADABLE PLD, 10 ns, PBGA484
封裝: 23 X 23 MM, 1.60 MM HEIGHT, 1 MM PITCH, FBGA-484
文件頁(yè)數(shù): 25/86頁(yè)
文件大?。?/td> 1212K
代理商: CY39100Z484-125BBI
Delta39K ISR
CPLD Family
Document #: 38-03039 Rev. *H
Page 25 of 86
Switching Waveforms
(continued)
Registered Output with Synchronous Clocking (Macrocell)
t
MCS
INPUT
SYNCHRONOUS
t
MCCO
REGISTERED
OUTPUT
t
MCH
CLOCK
Registered Input in I/O Cell
t
IOS
DATA
INPUT
INPUT REGISTER
CLOCK
t
IOCO
REGISTERED
OUTPUT
t
IOH
Clock to Clock
INPUT REGISTER
CLOCK
MACROCELL
REGISTER CLOCK
t
SCS
t
ICS
PT Clock to PT Clock
DATA
INPUT
PT CLOCK
t
SCS2PT
t
MCSPT
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CY39100Z484-125BGC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39100Z676-125BBC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39100Z676-125BBI 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39100Z676-125BGC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39100Z676-125BGI 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities