參數(shù)資料
型號(hào): CY39100V208-181MGI
廠商: Cypress Semiconductor Corp.
英文描述: CUTTERS, SIDE MINI BEVEL 125MMCUTTERS, SIDE MINI BEVEL 125MM; Capacity, cutting copper wire:1.5mm; Length:125mm; Capacity, cutting hard wire:0.4mm; Capacity, cutting soft iron:1.0mm; Edge Finish/Profile:Mini Bevel; Head type:Oval;
中文描述: CPLD器件在FPGA的密度
文件頁(yè)數(shù): 9/86頁(yè)
文件大小: 1212K
代理商: CY39100V208-181MGI
Delta39K ISR
CPLD Family
Document #: 38-03039 Rev. *H
Page 9 of 86
I/O Banks
The Delta39K interfaces the horizontal and vertical routing
channels to the pins through I/O banks. There are eight I/O
banks per device as shown in
Figure 7
, and all I/Os from an
I/O bank are located in the same section of a package for PCB
layout convenience.
Delta39K devices support True Vertical Migration (i.e., for
each package type, Delta39K devices of different densities
keep given pins in the same I/O banks). This allows for easy
and simple implementation of multiple I/O standards during the
design and prototyping phase, before a final density has been
determined. Please refer to the application note titled
“Family,
Package and Density Migration in Delta 39K and Quantum38K
CPLDs.”
Each I/O bank contains several I/O cells, and each I/O cell
contains an input/output register, an output enable register,
programmable slew rate control and programmable bus hold
control logic. Each I/O cell drives a pin output of the device;
the cell also supplies an input to the device that connects to a
dedicated track in the associated routing channel.
Each I/O bank can use any supported I/O standard by
supplying appropriate V
REF
and V
CCIO
voltages and config-
uring the I/O through the Warp software. All the V
REF
and
V
CCIO
pins in an I/O bank must be connected to the same V
REF
and V
CCIO
voltage respectively. This requirement restricts the
number of I/O standards supported by an I/O bank at any given
time.
The number of I/Os which can be used in each I/O bank
depend on the type of I/O standards and the number of V
CCIO
and GND pins being used. This restriction is derived from the
electromigration limit of the V
CCIO
and GND bussing on the
chip. Please refer to the note on page 17 and the application
note titled
“Delta39K Family Device I/O Standards and Config-
urations”
for details.
I/O Cell
Figure 8
is a block diagram of the Delta39K I/O cell. The I/O
cell contains a three-state input buffer, an output buffer, and a
register that can be configured as an input or output register.
The output buffer has a slew rate control option that can be
used to configure the output for a slower slew rate. The input
of the device and the pin output can each be configured as
registered or combinatorial; however, only one path can be
configured as registered in a given design.
The output enable in an I/O cell can be selected from one of
the four global control signals or from one of two Output
Control Channel (OCC) signals. The output enable can be
configured as always enabled or always disabled or it can be
controlled by one of the remaining inputs to the mux. The
selection is done via a mux that includes V
CC
and GND as
inputs.
Figure 6. Block Diagram of Channel Memory Block
4096-bit Dual-Port
Array
Configurable as
Async/Sync Dual-Port
or Sync FIFO
Configurable as
4K x 1, 2K x 2, 1K x 4,
and 512 x 8 block sizes
Horizontal Channel
All channel memory
inputs are driven from
the routing channels
All channel memory outputs
drive dedicated tracks in the
routing channels
GCLK[3:0]
Global Clock
Signals
V
Delta39K
b
b
b
bank 2
bank 3
bank 6
bank 7
Figure 7. Delta39K I/O Bank Block Diagram
相關(guān)PDF資料
PDF描述
CY39100V208-181NC CUTTERS, SIDE EXTRA FULL FLUSH 125MMCUTTERS, SIDE EXTRA FULL FLUSH 125MM; Capacity, cutting copper wire:1.5mm; Length:125mm; Capacity, cutting soft iron:1.0mm; Edge Finish/Profile:Extra Full Flush; Head type:Oval; Length, jaw
CY39100V208-181NI CUTTERS, SIDE FULL FLUSH 125MMCUTTERS, SIDE FULL FLUSH 125MM; Capacity, cutting copper wire:1.5mm; Length:125mm; Capacity, cutting soft iron:1.0mm; Edge Finish/Profile:Full Flush; Head type:Oval; Length, jaw:13mm
CY39100V208-181NTC PLIERS, SNIPE NOSE SERATED JAW 165MMPLIERS, SNIPE NOSE SERATED JAW 165MM; Jaw type:Snipe nose; Length:165mm; Handle type:ESD; Capacity, cutting copper wire:40mm; Finish:Serrated; Length, jaw:40mm
CY39100V208-181NTI CUTTERS, SIDE FULL FLUSHCUTTERS, SIDE FULL FLUSH; Capacity, cutting copper wire:1mm; Length:120mm; Capacity, cutting soft iron:0.6mm; Edge Finish/Profile:Full Flush; Head type:Tapered; Length, jaw:9mm
CY39100V208-200BBC CUTTERS, SIDE MINI BEVEL 125MMCUTTERS, SIDE MINI BEVEL 125MM; Capacity, cutting copper wire:1.2mm; Length:125mm; Capacity, cutting hard wire:0.4mm; Capacity, cutting soft iron:1.0mm; Edge Finish/Profile:Mini Bevel; Head type:Tapered;
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY39100V208-181NC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39100V208-181NI 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39100V208-181NTC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39100V208-181NTI 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39100V208-200BBC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities