參數(shù)資料
型號(hào)： CY39100V208-181MBI
廠商： Cypress Semiconductor Corp.
英文描述： PLIERS, SNIPE NOSE SERR JAW 125MMPLIERS, SNIPE NOSE SERR JAW 125MM; Jaw type:Snipe nose; Length:125mm; Handle type:Static Dissipative; Finish:Serrated; Length, jaw:20mm
中文描述： CPLD器件在FPGA的密度
文件頁(yè)數(shù)： 22/86頁(yè)
文件大?。?/td> 1212K
代理商： CY39100V208-181MBI
Delta39K ISR
CPLD Family
Document #: 38-03039 Rev. *H
Page 22 of 86
Input and Output Standard Timing Delay
Adjustments
All the timing specifications in this data sheet are specified
based on LVCMOS compliant inputs and outputs (fast slew
rates).
[15]
Apply following adjustments if the inputs and outputs
are configured to operate at other standards.
t
INDUTY
f
PLLO[14]
f
PLLI[14]
f
PLLVCO
P
SAPLLI
f
MPLLI
JTAG Parameters
t
JCKH
t
JCKL
t
JCP
t
JSU
t
JH
t
JCO
t
JXZ
t
JZX
40
6.2
12.5
100
–0.3
60
266
133
266
+0.3
50
40
6.2
12.5
100
–0.3
60
266
133
266
+0.3
50
40
6.2
12.5
100
–0.3
60
266
133
266
+0.3
50
40
6.2
12.5
100
–0.3
60
200
100
266
+0.3
50
40
6.2
12.5
100
–0.3
60
200
100
266
+0.3
50
%
MHz
MHz
MHz
%
KHz
25
25
50
10
10
25
25
50
10
10
25
25
50
10
10
25
25
50
10
10
25
25
50
10
10
ns
ns
ns
ns
ns
ns
ns
ns
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
Switching Characteristics — Parameter Values
Over the Operating Range (continued)
Parameter
233
200
181
125
83
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
I/O Standard
LVTTL – 2 mA
LVTTL – 4 mA
LVTTL – 6 mA
LVTTL – 8 mA
LVTTL – 12 mA
LVTTL – 16 mA
LVTTL – 24 mA
LVCMOS
LVCMOS3
LVCMOS2
LVCMOS18
3.3V PCI
GTL+
SSTL3 I
SSTL3 II
Output Delay Adjustments
Input Delay Adjustments
t
IOIN
t
CKIN
0
0
0
0
0
0
0
0
0.1
0.1
0.2
0.2
0.5
0.4
0
0.5
0.4
0.5
0.3
0.5
0.3
Fast Slew Rate
t
EA
2.75
1.8
1.8
1.2
0.6
0.16
0
0
0.14
0.05
0.41
1.6
–0.14
0.02
[16]
0.6
[16]
–0.15
–0.4
Slow Slew Rate
(additional delay to fast slew rate)
t
IODSLOW
t
EASLOW
2.6
2.0
2.5
2.0
2.5
2.0
2.4
2.0
2.3
2.0
2.0
2.0
1.6
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.1
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
t
IOD
t
ER
t
ERSLOW
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
t
IOREGPIN
0
0
0
0
0
0
0
0
0.2
0.4
0.3
0
0.2
0.3
0.3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0.1
0.7
0
0.1
0
0.9
[16]
0.1
0
0
0.3
0.2
Notes:
14. Refer to page 11 and the application note titled
“Delta39K PLL and Clock Tree”
for details on the PLL operation.
15. For “slow slew rate” output delay adjustments, refer to
Warp
software’s static timing analyzer results.
16. These delays are based on falling edge output. The rising edge delay depends on the size of pull-up resistor and termination voltage.
相關(guān)PDF資料
PDF描述
CY39100V208-181MGI CUTTERS, SIDE MINI BEVEL 125MMCUTTERS, SIDE MINI BEVEL 125MM; Capacity, cutting copper wire:1.5mm; Length:125mm; Capacity, cutting hard wire:0.4mm; Capacity, cutting soft iron:1.0mm; Edge Finish/Profile:Mini Bevel; Head type:Oval;
CY39100V208-181NC CUTTERS, SIDE EXTRA FULL FLUSH 125MMCUTTERS, SIDE EXTRA FULL FLUSH 125MM; Capacity, cutting copper wire:1.5mm; Length:125mm; Capacity, cutting soft iron:1.0mm; Edge Finish/Profile:Extra Full Flush; Head type:Oval; Length, jaw
CY39100V208-181NI CUTTERS, SIDE FULL FLUSH 125MMCUTTERS, SIDE FULL FLUSH 125MM; Capacity, cutting copper wire:1.5mm; Length:125mm; Capacity, cutting soft iron:1.0mm; Edge Finish/Profile:Full Flush; Head type:Oval; Length, jaw:13mm
CY39100V208-181NTC PLIERS, SNIPE NOSE SERATED JAW 165MMPLIERS, SNIPE NOSE SERATED JAW 165MM; Jaw type:Snipe nose; Length:165mm; Handle type:ESD; Capacity, cutting copper wire:40mm; Finish:Serrated; Length, jaw:40mm
CY39100V208-181NTI CUTTERS, SIDE FULL FLUSHCUTTERS, SIDE FULL FLUSH; Capacity, cutting copper wire:1mm; Length:120mm; Capacity, cutting soft iron:0.6mm; Edge Finish/Profile:Full Flush; Head type:Tapered; Length, jaw:9mm
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY39100V208-181MGC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39100V208-181MGI 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39100V208-181NC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39100V208-181NI 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39100V208-181NTC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
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