參數(shù)資料
型號： CY39100V208-181BGC
廠商： Cypress Semiconductor Corp.
英文描述： PLIERS, FLAT NOSE SMOOTH JAW 135MMPLIERS, FLAT NOSE SMOOTH JAW 135MM; Jaw type:Flat nose; Length:135mm; Handle type:ESD; Finish:Smooth; Length, jaw:22mm
中文描述： CPLD器件在FPGA的密度
文件頁數(shù)： 12/86頁
文件大?。?/td> 1212K
代理商： CY39100V208-181BGC
Delta39K ISR
CPLD Family
Document #: 38-03039 Rev. *H
Page 12 of 86
Table 6
describes the valid phase shift options that can be
used with or without an external feedback.
Table 7
is an example of the effect of all the available divide
and phase shift options on a VCO output of 250 MHz. It also
shows the effect of division on the duty cycle of the resultant
clock. Note that the duty cycle is 50-50 when a VCO output is
divided by an even number. Also note that the phase shift
applies to the VCO output and not to the divided output.
For more details on the architecture and operation of this PLL
please refer to the application note entitled
“Delta39K PLL and
Clock Tree”.
Table 4. Valid PLL Multiply and Divide Options—without External Feedback
Input Frequency
(GCLK[0])
f
PLLI
(MHz)
DC–12.5
100–133
50–133
33.3–88.7
25–66
20–53.2
16.6–44.3
12.5–33
12.5–16.625
Valid Multiply Options
VCO Output
Frequency (MHz)
N/A
1
100–133
2
100–266
3
100–266
4
100–266
5
100–266
6
100–266
8
100–266
16
200–266
Valid Divide Options
Output Frequency (INTCLK[3:0])
f
PLLO
(MHz)
DC–12.5
6.25–133
6.25–266
6.25–266
6.25–266
6.25–266
6.25–266
6.25–266
6.25–266
Value
Value
N/A
1–6, 8, 16
1–6, 8, 16
1–6, 8, 16
1–6, 8, 16
1–6, 8, 16
1–6, 8, 16
1–6, 8, 16
1–6, 8, 16
Off-chip Clock
Frequency
DC–6.25
3.125–66
3.125–133
3.1–266
3.125–133
3.1–133
3.1–133
3.125–133
3.125–133
N/A
Table 5. Valid PLL Multiply and Divide Options—With External Feedback
Input (GCLK) Frequency
f
PLLI
(MHz)
50–133
25–66.5
16.67–44.33
12.5–33.25
12.5–26.6
12.5–22.17
12.5–16.63
Valid Multiply Options
VCO Output
Frequency (MHz)
1
100–266
1
100–266
1
100–266
1
100–266
1
125–266
1
150–266
1
200–266
Valid Divide Options
Output (INTCLK) Frequency
f
PLLO
(MHz)
100–266
50–133
33.33–88.66
25–66.5
25–53.2
25–44.34
25–33.25
Value
Value
1
2
3
4
5
6
8
Off-chip Clock
Frequency
50–133
25–66.5
16.67–44.33
12.5–33.25
12.5–26.6
12.5–22.17
12.5–16.63
Table 6. Recommended PLL Phase Shift Options
Without External Feedback
With External Feedback
0°,45°, 90°, 135°, 180°, 225°, 270°, 315°
0°
Table 7. Timing of Clock Phases for all Divide Options for a V
CO
Output Frequency of 250 MHz
Divide
Factor
(ns)
Duty Cycle%
(ns)
(ns)
1
4
40–60
0
0.5
2
8
50
0
0.5
3
12
33–67
0
0.5
4
16
50
0
0.5
5
20
40–60
0
0.5
6
24
50
0
0.5
8
32
50
0
0.5
16
64
50
0
0.5
Period
0°
45°
90°
(ns)
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
135°
(ns)
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
180°
(ns)
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
225°
(ns)
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
270°
(ns)
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
315°
(ns)
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
相關(guān)PDF資料
PDF描述
CY39100V208-181BGI PLIERS, SNIPE NOSE SMOOTH JAW 135MMPLIERS, SNIPE NOSE SMOOTH JAW 135MM; Jaw type:Snipe nose; Length:135mm; Handle type:ESD; Finish:Smooth; Length, jaw:22mm
CY39100V208-181MBC PLIERS, SNIPE NOSE SERRATED JAW 135MMPLIERS, SNIPE NOSE SERRATED JAW 135MM; Jaw type:Snipe nose; Length:145mm; Handle type:ESD; Capacity, cutting copper wire:32mm; Finish:Serrated; Length, jaw:32mm
CY39100V208-181MBI PLIERS, SNIPE NOSE SERR JAW 125MMPLIERS, SNIPE NOSE SERR JAW 125MM; Jaw type:Snipe nose; Length:125mm; Handle type:Static Dissipative; Finish:Serrated; Length, jaw:20mm
CY39100V208-181MGI CUTTERS, SIDE MINI BEVEL 125MMCUTTERS, SIDE MINI BEVEL 125MM; Capacity, cutting copper wire:1.5mm; Length:125mm; Capacity, cutting hard wire:0.4mm; Capacity, cutting soft iron:1.0mm; Edge Finish/Profile:Mini Bevel; Head type:Oval;
CY39100V208-181NC CUTTERS, SIDE EXTRA FULL FLUSH 125MMCUTTERS, SIDE EXTRA FULL FLUSH 125MM; Capacity, cutting copper wire:1.5mm; Length:125mm; Capacity, cutting soft iron:1.0mm; Edge Finish/Profile:Extra Full Flush; Head type:Oval; Length, jaw
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY39100V208-181BGI 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39100V208-181MBC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39100V208-181MBI 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39100V208-181MGC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39100V208-181MGI 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
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