參數(shù)資料
型號(hào)： CY39100V208-181BBI
廠商： Cypress Semiconductor Corp.
英文描述： CUTTERS, SIDE FULL FLUSH 120MMCUTTERS, SIDE FULL FLUSH 120MM; Capacity, cutting copper wire:1mm; Length:120mm; Capacity, cutting soft iron:0.6mm; Edge Finish/Profile:Full Flush; Head type:Tapered/Relieved; Length, jaw:9mm
中文描述： CPLD器件在FPGA的密度
文件頁(yè)數(shù)： 17/86頁(yè)
文件大?。?/td> 1212K
代理商： CY39100V208-181BBI
Delta39K ISR
CPLD Family
Document #: 38-03039 Rev. *H
Page 17 of 86
Capacitance
Power-up Sequence Requirements
Upon power-up, all the outputs remain three-stated until all
the V
pins
have powered-up to the nominal voltage and
the part has completed configuration.
The part will not start configuration until V
CC
, V
CCIO
,
V
CCJTAG
, V
CCCNFG
, V
CCPLL
and V
CCPRG
have reached
nominal voltage.
V
CC
pins can be powered up in any order. This includes
V
CC
, V
CCIO
, V
CCJTAG
, V
CCCNFG
, V
CCPLL
and V
CCPRG
.
All V
s on a bank should be tied to the same potential
and powered up together.
All V
s (even the unused banks) need to be powered up
to at least 1.5V before configuration has completed.
Maximum ramp time for all V
CC
s should be 0V to nominal
voltage in 100 ms.
Notes:
9.
PCI spec (rev 2.2) requires the IDSEL pin to have capacitance less than or equal to 8 pF. Delta39K Pin Tables starting from page 45, identify all the I/O pins in
a given package, which can be used as IDSEL in a PCI design. All other I/O pins meet the PCI requirement of capacitance less than or equal to 10 pf.
10. The number of I/Os which can be used in each I/O bank depends on the type of I/O standards and the number of V
CCIO
and GND pins being used. Please refer
to the application note titled
“Delta39K and Quantum38K I/O Standards and Configurations”
for details.
The source current limit per I/O bank per Vccio pin is 165 mA.
The sink current limit per I/O bank per GND pin is 230 mA.
11.
See “Power-up Sequence Requirements” below for V
CCIO
requirement.
12. 25W resistor terminated to termination voltage of 1.5V.
Parameter
Description
Test Conditions
Min.
Max.
10
12
8
Unit
pF
pF
pF
C
I/O
C
CLK
C
PCI
Input/Output Capacitance
Clock Signal Capacitance
PCI-compliant
[9]
Capacitance
V
in
= V
CCIO
@ f = 1 MHz 25°C
V
in
= V
CCIO
@ f = 1 MHz 25°C
V
in
= V
CCIO
@ f = 1 MHz 25°C
5
DC Characteristics (I/O)
[10]
I/O Standards
LVTTL –2 mA
LVTTL –4 mA
LVTTL –6 mA
LVTTL –8 mA
LVTTL –12 mA
LVTTL –16 mA
LVTTL –24 mA
LVCMOS
LVCMOS3
V
(V)
N/A
V
(V)
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.0
2.5
V
OH
(V)
V
OL
(V)
V
IH
(V)
V
IL
(V)
@ I
OH
=
–2 mA
–4 mA
–6 mA
–8 mA
–12 mA
–16 mA
–24 mA
–0.1 mA
–0.1 mA
–0.1 mA
–1.0 mA
–2.0 mA
–2 mA
–0.5 mA
V
OH
(min.)
2.4
2.4
2.4
2.4
2.4
2.4
2.4
V
CCIO
– 0.2V
V
CCIO
– 0.2V
2.1
2.0
1.7
V
CCIO
– 0.45V
0.9V
CCIO
@ I
OL
=
2 mA
4 mA
6 mA
8 mA
12 mA
16 mA
24 mA
0.1 mA
0.1 mA
0.1 mA
1.0 mA
2.0 mA
2.0 mA
1.5 mA
36 mA
[12]
8 mA
16 mA
7.6 mA
V
(max.)
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.2
0.2
0.2
0.4
0.7
0.45
0.1V
CCIO
0.6
0.7
0.5
0.54
0.35
0.4
0.4
0.4
0.4
Min.
2.0V
2.0V
2.0V
2.0V
2.0V
2.0V
2.0V
2.0V
2.0V
1.7V
Max.
Min.
Max.
0.8V
0.8V
0.8V
0.8V
0.8V
0.8V
0.8V
0.8V
0.8V
0.7V
V
CCIO
+ 0.3 –0.3V
V
CCIO
+ 0.3 –0.3V
V
CCIO
+ 0.3 –0.3V
V
CCIO
+ 0.3 –0.3V
V
CCIO
+ 0.3 –0.3V
V
CCIO
+ 0.3 –0.3V
V
CCIO
+ 0.3 –0.3V
V
CCIO
+ 0.3 –0.3V
V
CCIO
+ 0.3 –0.3V
V
CCIO
+ 0.3 –0.3V
LVCMOS2
LVCMOS18
3.3V PCI
GTL+
SSTL3 I
SSTL3 II
SSTL2 I
SSTL2 II
HSTL I
HSTL II
HSTL III
HSTL IV
1.8
3.3
[11]
0.65V
CCIO
0.5V
CCIO
V
REF
+ 0.2
V
REF
+ 0.2
V
REF
+ 0.2
V
REF
+ 0.18 V
CCIO
+ 0.3 –0.3V V
REF
– 0.18
V
REF
+ 0.18 V
CCIO
+ 0.3 –0.3V V
REF
– 0.18
V
REF
+ 0.1
V
CCIO
+ 0.3 –0.3V
V
REF
+ 0.1
V
CCIO
+ 0.3 –0.3V
V
REF
+ 0.1
V
CCIO
+ 0.3 –0.3V
V
REF
+ 0.1
V
CCIO
+ 0.3 –0.3V
V
CCIO
+ 0.3 –0.3V
V
CCIO
+ 0.5 –0.5V
0.35V
CCIO
0.3V
CCIO
V
REF
– 0.2
V
REF
– 0.2
V
REF
– 0.2
1.0
1.5
1.5
1.25
1.25
0.75
0.75
0.9
0.9
3.3
3.3
2.5
2.5
1.5
1.5
1.5
1.5
–8 mA
–16 mA
–7.6 mA V
CCIO
– 0.62V
–15.2 mA V
CCIO
– 0.43V 15.2 mA
–8 mA
V
CCIO
– 0.4V
–16 mA
V
CCIO
– 0.4V
–8 mA
V
CCIO
– 0.4V
–8 mA
V
CCIO
– 0.4V
V
CCIO
– 1.1V
V
CCIO
– 0.9V
V
CCIO
+ 0.3 –0.3V
V
CCIO
+ 0.3 –0.3V
8 mA
16 mA
24 mA
48 mA
V
REF
– 0.1
V
REF
– 0.1
V
REF
– 0.1
V
REF
– 0.1
Configuration Parameters
Parameter
t
RECONFIG
Description
Min.
200
Unit
ns
Reconfig
pin LOW time before it goes HIGH
相關(guān)PDF資料
PDF描述
CY39100V208-181BGC PLIERS, FLAT NOSE SMOOTH JAW 135MMPLIERS, FLAT NOSE SMOOTH JAW 135MM; Jaw type:Flat nose; Length:135mm; Handle type:ESD; Finish:Smooth; Length, jaw:22mm
CY39100V208-181BGI PLIERS, SNIPE NOSE SMOOTH JAW 135MMPLIERS, SNIPE NOSE SMOOTH JAW 135MM; Jaw type:Snipe nose; Length:135mm; Handle type:ESD; Finish:Smooth; Length, jaw:22mm
CY39100V208-181MBC PLIERS, SNIPE NOSE SERRATED JAW 135MMPLIERS, SNIPE NOSE SERRATED JAW 135MM; Jaw type:Snipe nose; Length:145mm; Handle type:ESD; Capacity, cutting copper wire:32mm; Finish:Serrated; Length, jaw:32mm
CY39100V208-181MBI PLIERS, SNIPE NOSE SERR JAW 125MMPLIERS, SNIPE NOSE SERR JAW 125MM; Jaw type:Snipe nose; Length:125mm; Handle type:Static Dissipative; Finish:Serrated; Length, jaw:20mm
CY39100V208-181MGI CUTTERS, SIDE MINI BEVEL 125MMCUTTERS, SIDE MINI BEVEL 125MM; Capacity, cutting copper wire:1.5mm; Length:125mm; Capacity, cutting hard wire:0.4mm; Capacity, cutting soft iron:1.0mm; Edge Finish/Profile:Mini Bevel; Head type:Oval;
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY39100V208-181BGC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39100V208-181BGI 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39100V208-181MBC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39100V208-181MBI 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39100V208-181MGC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
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