參數(shù)資料
型號(hào)： CY39100V208-125NTC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： PLD
英文描述： WIRE STRIPPER, 0.30MMWIRE STRIPPER, 0.30MM; Stripping Capacity:0.3mm
中文描述： LOADABLE PLD, 10 ns, PQFP208
封裝： THERMALLY ENHANCED, QFP-208
文件頁數(shù)： 3/86頁
文件大?。?/td> 1212K
代理商： CY39100V208-125NTC
Delta39K ISR
CPLD Family
Document #: 38-03039 Rev. *H
Page 3 of 86
General Description
The Delta39K family, based on a 0.18-mm
,
six-layer metal
CMOS logic process, offers a wide range of high-density
solutions at unparalleled system performance. The Delta39K
family is designed to combine the high speed, predictable
timing, and ease of use of CPLDs with the high densities and
low power of FPGAs. With devices ranging from 30,000 to
200,000 usable gates, the family features devices ten times
the size of previously available CPLDs. Even at these large
densities, the Delta39K family is fast enough to implement a
fully synthesizable 64-bit, 66-MHz PCI core.
The architecture is based on Logic Block Clusters (LBC) that
are connected by Horizontal and Vertical (H and V) routing
channels. Each LBC features eight individual Logic Blocks
(LB) and two cluster memory blocks. Adjacent to each LBC is
a channel memory block, which can be accessed directly from
the I/O pins. Both types of memory blocks are highly config-
urable and can be cascaded in width and depth. See
Figure 1
for a block diagram of the Delta39K architecture.
All the members of the Delta39K family have Cypress’s highly
regarded In-System Reprogrammability (ISR) feature, which
simplifies both design and manufacturing flows, thereby
reducing costs. The ISR feature provides the ability to recon-
4
GCLK[3:0]
4
4
4
Channel
RAM
4
GCLK[3:0]
4
4
4
4
GCLK[3:0]
4
4
4
4
4
GCLK[3:0]
PLL and Clock MUX
GCTL[3:0]
I/O Bank 6
I/O Bank 7
I/O Bank 3
I/O Bank 2
I
I
I
I
LB 4
LB 3
LB 0
Cluster
RAM
LB 5
LB 6
LB 7
LB 2
LB 1
PIM
Cluster
RAM
Channel
RAM
Channel
RAM
Channel
RAM
Channel
RAM
Channel
RAM
Channel
RAM
Channel
RAM
Channel
RAM
Channel
RAM
Channel
RAM
Channel
RAM
LB 4
LB 3
LB 0
Cluster
RAM
LB 5
LB 6
LB 7
LB 2
LB 1
PIM
Cluster
RAM
LB 4
LB 3
LB 0
Cluster
RAM
LB 5
LB 6
LB 7
LB 2
LB 1
PIM
Cluster
RAM
LB 4
LB 3
LB 0
Cluster
RAM
LB 5
LB 6
LB 7
LB 2
LB 1
PIM
RAM
LB 4
LB 3
LB 0
Cluster
RAM
LB 5
LB 6
LB 7
LB 2
LB 1
PIM
Cluster
RAM
LB 4
LB 3
LB 0
Cluster
RAM
LB 5
LB 6
LB 7
LB 2
LB 1
PIM
Cluster
RAM
LB 4
LB 3
LB 0
RAM
LB 5
LB 6
LB 7
LB 2
LB 1
PIM
RAM
LB 4
LB 3
LB 0
Cluster
RAM
LB 5
LB 6
LB 7
LB 2
LB 1
PIM
RAM
LB 4
LB 3
LB 0
Cluster
RAM
LB 5
LB 6
LB 7
LB 2
LB 1
PIM
Cluster
RAM
LB 4
LB 3
LB 0
Cluster
RAM
LB 5
LB 6
LB 7
LB 2
LB 1
PIM
Cluster
RAM
LB 4
LB 3
LB 0
Cluster
RAM
LB 5
LB 6
LB 7
LB 2
LB 1
PIM
RAM
LB 4
LB 3
LB 0
RAM
LB 5
LB 6
LB 7
LB 2
LB 1
PIM
RAM
Figure 1. Delta39K100 Block Diagram (Three Rows × Four Columns) with I/O Bank Structure
相關(guān)PDF資料
PDF描述
CY39100V208-125NTI WIRE STRIPPER, 0.40MMWIRE STRIPPER, 0.40MM; Stripping Capacity:0.4mm
CY39100V208-181BBC CUTTERS, SIDE EXTRA FULL FLUSH 120MMCUTTERS, SIDE EXTRA FULL FLUSH 120MM; Capacity, cutting copper wire:1mm; Length:120mm; Capacity, cutting soft iron:0.6mm; Edge Finish/Profile:Extra Full Flush; Head type:Tapered/Relieved; Length,
CY39100V208-181BBI CUTTERS, SIDE FULL FLUSH 120MMCUTTERS, SIDE FULL FLUSH 120MM; Capacity, cutting copper wire:1mm; Length:120mm; Capacity, cutting soft iron:0.6mm; Edge Finish/Profile:Full Flush; Head type:Tapered/Relieved; Length, jaw:9mm
CY39100V208-181BGC PLIERS, FLAT NOSE SMOOTH JAW 135MMPLIERS, FLAT NOSE SMOOTH JAW 135MM; Jaw type:Flat nose; Length:135mm; Handle type:ESD; Finish:Smooth; Length, jaw:22mm
CY39100V208-181BGI PLIERS, SNIPE NOSE SMOOTH JAW 135MMPLIERS, SNIPE NOSE SMOOTH JAW 135MM; Jaw type:Snipe nose; Length:135mm; Handle type:ESD; Finish:Smooth; Length, jaw:22mm
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY39100V208-125NTI 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39100V208-181BBC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39100V208-181BBI 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39100V208-181BGC 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
CY39100V208-181BGI 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities
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