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參數(shù)資料
| 型號： | CY39100V208-125BBI |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | CUTTER & PLIER SET, SENSO PLUS 6 PIECE; |
| 中文描述： | CPLD器件在FPGA的密度 |
| 文件頁數(shù)： | 37/86頁 |
| 文件大?。?/td> | 1212K |
| 代理商： | CY39100V208-125BBI |
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Delta39K ISR
CPLD Family
Document #: 38-03039 Rev. *H
Page 37 of 86
Switching Waveforms
(continued)
Channel Memory Synchronous FIFO Master Reset Timing
MASTER
RESET INPUT
READ ENABLE /
WRITE ENABLE
EMPTY/FULL
PROGRAMMABLE
ALMOST EMPTY
t
CHMFRS
t
CHMFRSR
t
CHMFRSF
t
CHMFRSF
t
CHMFRSF
HALF-FULL/
PROGRAMMABLE
ALMOST FULL
REGISTERED
OUTPUT
FLAGS
FLAGS
Pin Count
208 = 208 Leads
256 = 256 Balls
388 = 388 Balls
484 = 484 Balls
676 = 676 Balls
C Y 3 9 1 0 0 V 6 7 6 - 2 0 0 M B C
Cypress Semiconductor ID
Family Type
39 = Delta39K Family
Gate Density
30=30k Usable Gates
50=50k Usable Gates
100=100k Usable Gates
165 = 165k Usable Gates
200 = 200k Usable Gates
Speed
233 = 233 MHz 125 = 125 MHz
200 = 200 MHz 83 = 83 MHz
181 = 181 MHz
Package Type
N = Plastic Quad Flat Pack (PQFP)
NT = Thermally Enhanced Quad Flat Pack (EQFP)
BG = Ball Grid Array (BGA)
BB = Fine-pitch Ball Grid Array (FBGA)
1.0-mm Lead Pitch
MG = Self-Boot Solution -- Ball Grid Array
MB = Self-Boot Solution -- Fine Pitch Ball Grid Array
1.0-mm Lead Pitch
Operating Conditions
Commercial
Industrial
0°C to +70°C
--40°C to +85°C
Operating Reference Voltage
V = 3.3V or 2.5V Supply Voltage
Z = 1.8V Supply Voltage
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY39100V208-125BGC | CPLDs at FPGA Densities |
| CY39100V208-125BGI | HAND TOOL KIT, 14 PC; |
| CY39100V208-125MBC | PLIERS, CIRCLIP ADJUSTABLEPLIERS, CIRCLIP ADJUSTABLE; Handle type:Soft grip |
| CY39100V208-125MBI | PLIERS, ULTRA FLAT FINE SMOOTH JAW 135MMPLIERS, ULTRA FLAT FINE SMOOTH JAW 135MM; Jaw type:Flat nose; Length:135mm; Handle type:ESD; Finish:Smooth; Length, jaw:22mm |
| CY39100V208-125MGC | CUTTERS, SIDE SEMI FLUSH 180MMCUTTERS, SIDE SEMI FLUSH 180MM; Capacity, cutting copper wire:4mm; Length:180mm; Angle, blade:15(degree); Capacity, cutting piano wire:2mm; Edge Finish/Profile:Semi Flush |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY39100V208-125BGC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY39100V208-125BGI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY39100V208-125MBC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY39100V208-125MBI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY39100V208-125MGC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
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