參數(shù)資料
型號： CY37512VP256-66BGI
英文描述： Electrically-Erasable Complex PLD
中文描述： 電可擦除復雜可編程邏輯器件
文件頁數(shù)： 15/66頁
文件大?。?/td> 2069K
代理商： CY37512VP256-66BGI
Ultra37000 CPLD Family
Ultra37000: December 13, 1996
Revision: March 15, 2001
15
5.0V Device Electrical Characteristics
Over the Operating Range
Parameter
V
OH
Description
Test Conditions
I
OH
= –3.2 mA (Com’l/Ind)
[4]
I
OH
= –2.0 mA (Mil)
[4]
V
CC
= Max. I
OH
= 0
μ
A (Com’l)
[6]
I
OH
= 0
μ
A (Ind/Mil)
[6]
I
OH
= –100
μ
A (Com’l)
[6]
I
OH
= –150
μ
A (Ind/Mil)
[6]
V
CC
= Min.
I
OL
= 12 mA (Mil)
[4]
Guaranteed Input Logical HIGH Voltage
for all Inputs
[7]
Guaranteed Input Logical LOW Voltage
for all Inputs
[7]
V
I
= GND OR V
CC
, Bus-Hold Disabled
V
O
= GND or V
CC
, Output Disabled,
Bus-Hold Disabled
V
CC
= Max., V
OUT
= 0.5V
Min.
2.4
2.4
Typ.
Max.
Unit
V
V
V
V
V
V
V
V
V
Output HIGH Voltage
V
CC
= Min.
V
OHZ
Output HIGH Voltage with
Output Disabled
[5]
4.2
4.5
3.6
3.6
0.5
0.5
V
OL
Output LOW Voltage
I
OL
= 16 mA (Com’l/Ind)
[4]
V
IH
Input HIGH Voltage
2.0
V
CCmax
V
IL
Input LOW Voltage
–0.5
0.8
V
I
IX
I
OZ
Input Load Current
Output Leakage Current
–10
–50
10
50
μ
A
μ
A
I
OS
Output Short Circuit
Current
[8, 5]
Input Bus-Hold LOW
Sustaining Current
Input Bus-Hold HIGH
Sustaining Current
Input Bus-Hold LOW Overdrive
Current
Input Bus-Hold HIGH Overdrive
Current
–30
–160
mA
I
BHL
V
CC
= Min., V
IL
= 0.8V
+75
μ
A
I
BHH
V
CC
= Min., V
IH
= 2.0V
–75
μ
A
I
BHLO
V
CC
= Max.
+500
μ
A
I
BHHO
V
CC
= Max.
–500
μ
A
Inductance
[5]
Parameter
L
Description
Maximum Pin
Inductance
Test
Conditions
V
IN
= 5.0V
at f = 1 MHz
44-
Lead
TQFP
2
44-
Lead
PLCC
5
44-
Lead
CLCC
2
84-
Lead
PLCC
8
84-
Lead
CLCC
5
100-
Lead
TQFP
8
160-
Lead
TQFP
9
208-
Lead
PQFP
11
Unit
nH
Capacitance
[5]
Parameter
Description
Test Conditions
Max.
10
12
16
Unit
pF
pF
pF
C
I/O
C
CLK
C
DP
Input/Output Capacitance
Clock Signal Capacitance
Dual Function Pins
[9]
V
IN
= 5.0V at f = 1 MHz at T
A
= 25
°
C
V
IN
= 5.0V at f = 1 MHz at T
A
= 25
°
C
V
IN
= 5.0V at f = 1 MHz at T
A
= 25
°
C
Endurance Characteristics
[5]
Parameter
Description
Test Conditions
Min.
1,000
Typ.
10,000
Unit
Cycles
N
Minimum Reprogramming Cycles
Normal Programming Conditions
[2]
Notes:
4.
5.
6.
I
= –2
mA, I
= 2 mA for TDO.
Tested initially and after any design or process changes that may affect these parameters.
When the I/O is output disabled, the bus-hold circuit can weakly pull the I/O to above 3.6V if no leakage current is allowed. Note that all I/Os are output disabled
during ISR programming. Refer to the application note “Understanding Bus-Hold” for additional information.
These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. V
OUT
= 0.5V has been chosen to avoid test
problems caused by tester ground degradation.
Dual pins are I/O with JTAG pins.
7.
8.
9.
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