
Ultra37000 CPLD Family
Document #: 38-03007 Rev. *C
Page 29 of 62
CY37064V
CY37128V
Typical 3.3V Power Consumption
(continued)
0
5
10
15
20
25
30
35
40
45
0
20
40
60
Frequency (MHz)
80
100
120
140
I
Low Power
High Speed
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
V
CC
= 3.3V, T
A
= Room Temperature
0
10
20
30
40
50
60
70
80
0
20
40
60
Frequency (M Hz)
80
100
120
140
I
Low Power
High Speed
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
V
CC
= 3.3V, T
A
= Room Temperature