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參數(shù)資料
| 型號(hào)： | CY37256VP208-100NC |
| 英文描述： | Electrically-Erasable Complex PLD |
| 中文描述： | 電可擦除復(fù)雜可編程邏輯器件 |
| 文件頁數(shù)： | 7/66頁 |
| 文件大?。?/td> | 2069K |
| 代理商： | CY37256VP208-100NC |
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Ultra37000 CPLD Family
Ultra37000: December 13, 1996
Revision: March 15, 2001
7
Clocking
Each I/O and buried macrocell has access to four synchronous
clocks (CLK0, CLK1, CLK2 and CLK3) as well as an asynchro-
nous product term clock PTCLK. Each input macrocell has
access to all four synchronous clocks.
Dedicated Inputs/Clocks
Five pins on each member of the Ultra37000 family are desig-
nated as input-only. There are two types of dedicated inputs
on Ultra37000 devices: input pins and input/clock pins.
Figure 3
illustrates the architecture for input pins. Four input
options are available for the user: combinatorial, registered,
double-registered, or latched. If a registered or latched option
is selected, any one of the input clocks can be selected for
control.
Figure 4
illustrates the architecture for the input/clock pins.
Like the input pins, input/clock pins can be combinatorial, reg-
istered, double-registered, or latched. In addition, these pins
feed the clocking structures throughout the device. The clock
path at the input has user-configurable polarity.
Product Term Clocking
In addition to the four synchronous clocks, the Ultra37000 fam-
ily also has a product term clock for asynchronous clocking.
Each logic block has an independent product term clock which
is available to all 16 macrocells. Each product term clock also
supports user configurable polarity selection.
Timing Model
One of the most important features of the Ultra37000 family is
the simplicity of its timing. All delays are worst case and sys-
tem performance is unaffected by the features used.
Figure 5
illustrates the true timing model for the 167-MHz devices in
high speed mode. For combinatorial paths, any input to any
output incurs a 6.5-ns worst-case delay regardless of the
amount of logic used. For synchronous systems, the input set-
up time to the output macrocells for any input is 3.5 ns and the
clock to output time is also 4.0 ns. These measurements are
for any output and synchronous clock, regardless of the logic
used.
The Ultra37000 features:
No fanout delays
No expander delays
No dedicated vs. I/O pin delays
No additional delay through PIM
No penalty for using 0–16 product terms
No added delay for steering product terms
No added delay for sharing product terms
No routing delays
No output bypass delays
The simple timing model of the Ultra37000 family eliminates
unexpected performance penalties.
JTAG and PCI Standards
PCI Compliance
5V operation of the Ultra37000 is fully compliant with the PCI
Local Bus Specification published by the PCI Special Interest
Group. The 3.3V products meet all PCI requirements except
for the output 3.3V clamp, which is in direct conflict with 5V
tolerance. The Ultra37000 family’s simple and predictable tim-
ing model ensures compliance with the PCI AC specifications
independent of the design.
Figure 4. Input/Clock Macrocell
0
1
2
3
O
C10C11
TO PIM
D
Q
D
Q
D
Q
LE
INPUT/CLOCK PIN
0
1
2
3
O
FROM CLOCK
POLARITY INPUT
CLOCK PINS
0
1
O
C12
TO CLOCK MUX ON
ALL INPUT MACROCELLS
TO CLOCK MUX
IN EACH
LOGIC BLOCK
0
1
CLOCK POLARITY MUX
ONE PER LOGIC BLOCK
FOR EACH CLOCK INPUT
C8 C9
C13, C14, C15
OR C16
O
Figure 5. Timing Model for CY37128
COMBINATORIAL SIGNAL
REGISTERED SIGNAL
D,T,L
O
CLOCK
INPUT
INPUT
OUTPUT
OUTPUT
t
S
= 3.5 ns
t
CO
= 4.5 ns
t
PD
= 6.5 ns
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY37256VP208-100NXC | 功能描述:IC CPLD 256 MACROCELL 208BQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:Ultra37000™ 標(biāo)準(zhǔn)包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時(shí)間 tpd(1):7.1ns 電壓電源 - 內(nèi)部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28） 包裝:托盤 |
| CY37256VP208-66NC | 制造商:Cypress Semiconductor 功能描述: 制造商:Rochester Electronics LLC 功能描述: |
| CY37256VP208-66NI | 制造商:Cypress Semiconductor 功能描述:CPLD Ultra37000 Family 7.7K Gates 256 Macro Cells 66MHz 3.3V 208-Pin PQFP |
| CY37256VP208-66NXC | 功能描述:IC CPLD 256 MACROCELL 208BQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:Ultra37000™ 標(biāo)準(zhǔn)包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時(shí)間 tpd(1):7.1ns 電壓電源 - 內(nèi)部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28） 包裝:托盤 |
| CY37256VP208-66NXI | 功能描述:IC CPLD 256 MACROCELL 208BQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - CPLD（復(fù)雜可編程邏輯器件） 系列:Ultra37000™ 標(biāo)準(zhǔn)包裝:24 系列:CoolRunner II 可編程類型:系統(tǒng)內(nèi)可編程 最大延遲時(shí)間 tpd(1):7.1ns 電壓電源 - 內(nèi)部:1.7 V ~ 1.9 V 邏輯元件/邏輯塊數(shù)目:24 宏單元數(shù):384 門數(shù):9000 輸入/輸出數(shù):173 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:208-BFQFP 供應(yīng)商設(shè)備封裝:208-PQFP（28x28） 包裝:托盤 |
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