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| 型號： | CY3138R62 |
| 英文描述： | Programmable Logic |
| 中文描述： | 可編程邏輯 |
| 文件頁數(shù)： | 3/7頁 |
| 文件大?。?/td> | 63K |
| 代理商： | CY3138R62 |
CY3130
Document #: 38-03050 Rev. *C
Page 3 of 7
ARCHITECTURE fsm OF drink IS
TYPE drinkState IS (zero,five,ten,fifteen,
twenty,twentyfive,owedime);
SIGNAL drinkstatus:drinkState;
BEGIN
PROCESS BEGIN
WAIT UNTIL clock = ’1’;
giveDrink <= ’0’;
returnDime <= ’0’;
returnNickel <= ’0’;
CASE drinkStatus IS
WHEN zero =>
IF (nickel = ’1’) THEN
drinkStatus <= five;
ELSIF (dime = ’1’) THEN
drinkStatus <= Ten;
ELSIF (quarter = ’1’) THEN
drinkStatus <= twentyfive;
END IF;
WHEN five =>
IF (nickel = ’1’) THEN
drinkStatus <= ten;
ELSIF (dime = ’1’) THEN
drinkStatus <= fifteen;
ELSIF (quarter = ’1’) THEN
giveDrink <= ’1’;
drinkStatus <= zero
END IF;
-- Several states are omitted in this
-- example. The omitted states are ten,
-- fifteen, twenty, and twentyfive.
WHEN owedime =>
returnDime <= ’1’;
drinkStatus <= zero;
when others =>
-- This makes sure that the state
-- machine resets itself if
-- it somehow gets into an undefined state.
drinkStatus <= zero;
END CASE;
END PROCESS;
END FSM;
VHDL is a strongly typed language. It comes with several
predefined operators, such as + and /= (add, not-equal-to).
VHDL offers the capability of defining multiple meanings for
operators (such as +), which results in simplification of the
code written. For example, the following code segment shows
that “count <= count +1” can be written such that count is a
std_logic_vector, and 1 is an integer.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.std_arith.all;
ENTITY sequence IS
port (clk: in std_logic;
s : inout std_logic);
end sequence;
ARCHITECTURE fsm OF sequence IS
SIGNAL count: std_logic_vector(3 downto 0);
BEGIN
PROCESS BEGIN
WAIT UNTIL clk = ’1’;
CASE count IS
WHEN x“0” | x“1” | x“2” | x“3” =>
s <= ’1’;
count <= count + 1;
WHEN x“4” | x“5” | x“6” | x“7” =>
s <= ’0’;
count <= count + 1;
WHEN x“8” | x“9” =>
s <= ’1’;
count <= count + 1;
WHEN others =>
s <= ’0’;
count <= (others => ’0’);
END CASE;
END PROCESS;
END FSM;
In this example, the + operator is overloaded to accept both
integer and std_logic arguments.
Warp
Enterprise supports
overloading operators.
Functions
A major advantage of VHDL is the ability to implement
functions. The support of functions allows designs to be
reused by simply specifying a function and passing the appro-
priate parameters.
Warp
Enterprise features some built-in
functions such as the truth-table function (ttf). The ttf is
particularly useful for state machine or look-up table
designs. The following code describes a seven-segment
display decoder implemented with the ttf:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.table_std.all;
ENTITY seg7 IS
PORT(
inputs: IN STD_LOGIC_VECTOR (0 to 3)
outputs: OUT STD_LOGIC_VECTOR (0 to 6)
);
END SEG7;
ARCHITECTURE mixed OF seg7 IS
CONSTANT truthTable:
ttf_table (0 to 11, 0 to 10) := (
-- input&
output
-- -----------------------
”0000”&
”0111111”,
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