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參數(shù)資料
| 型號： | CY3128R62 |
| 英文描述： | Programmable Logic |
| 中文描述： | 可編程邏輯 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大小： | 67K |
| 代理商： | CY3128R62 |
CY3120
Document #: 38-03049 Rev. *C
Page 6 of 8
MODULE half_adder(x, y, sum, carry);
INPUT x, y;
OUTPUT sum, carry;
ASSIGN sum = x^y;
ASSIGN carry = x&y;
ENDMODULE
Structural Verilog
While all of the design methodologies described thus far are
high-level entry methods, structural Verilog provides a method
for designing at a very low level. In structural descriptions, the
designer simply lists the components that make up the design
and specifies how the components are wired together.
Figure 5
displays the schematic of a simple 3-bit shift register
and the following code shows how this design can be
described in
Warp
using structural Verilog.
MODULE shifter3 (clk, x, q0, q1, q2);
INPUT clk, x;
OUTPUT q0, q1, q2;
WIRE q0, q1, q2;
REG q0_temp, q1_temp, q2_temp;
DFF d1(x,clk,q0_temp);
DFF d2(q0_temp,clk,q1_temp);
DFF d3(q1_temp,clk,q2_temp);
ASSIGN q0 = q0_temp;
ASSIGN q1 = q1_temp;
ASSIGN q2 = q2_temp;
ENDMODULE;
All of the design-entry methods described can be mixed as
desired. Verilog has the ability to combine both high- and
low-level entry methods in a single file. The flexibility and
power of Verilog allows users of
Warp
to describe designs
using whatever method is appropriate for their particular
design.
Finite State Machine Editor
Aldec’s Active-HDL FSM finite state machine editor, allows
graphic design entry through the use of graphical state
diagrams. A design may be represented graphically using
state diagrams and data flow logic. This tool will automatically
generate the HDL code of the design.
Compilation
Once the VHDL or Verilog description of the design is
complete, it is compiled using
Warp
. Although implementation
is with a single command, compilation is actually a multistep
process as shown in
Figure 1
. The first part of the compilation
process is the same for all devices. The input description is
synthesized to a logical representation of the design. Warp
synthesis is unique in that the input languages support
device-independent design descriptions. Competing program-
mable logic compilers require very specific and device-
dependent information in the design description.
Warp
synthesis is based on UltraGen technology. This
technology allows
Warp
to infer adders, subtractors, multi-
pliers, comparators, counters and shifters from the behavioral
descriptions.
Warp
then replaces these operators internally
with an architecture-specific circuit. This circuit or “module” is
also pre-optimized for either area or speed.
Warp
uses the
appropriate implementation based on user directives.
The second step of compilation is an iterative process of
optimizing the design and fitting the logic into the targeted
device. Logical optimization in
Warp
is accomplished using
Espresso algorithms. The optimized design is automatically
fed to the
Warp
fitter for targeting a PLD or CPLD. This fitter
supports the automatic or manual placement of pin assign-
ments as well as automatic selection of D or T flip-flops. After
optimization and fitting, Warp creates a JEDEC or Intel hex file
for the specified PLD or CPLD.
Automatic Error Tracking
Warp
features automatic error location that allows problems to
be diagnosed and corrected in seconds. Errors from compi-
lation are displayed immediately in a window. If the user
highlights a particular error,
Warp
will automatically open the
source code file and highlight the offending line in the entered
design. If the device fitting process includes errors, a window
will again describe them. A detailed report file is generated
indicating the resources required to fit the input design and any
problems that occurred in the process.
Simulation
Warp
includes a post-synthesis timing simulator called
Active-HDL Sim. Active-HDL Sim features a graphical
waveform simulator that can be used to simulate PLD/CPLD
designs generated in
Warp
. The simulator provides timing
simulation for PLDs/CPLDs and features interactive waveform
viewing as well as graphical creation of stimulus waveforms.
The simulator also provides the ability to probe internal nodes,
and automatically generate clocks and pulses. (Source level
simulation support is available with
Warp
Enterprise
[CY3130].)
Warp
will also output standard VHDL and Verilog timing
models. These models can be used with many third-party
simulators to perform functional and timing verifications of the
synthesized design.
Architecture Explorer
The Architecture Explorer graphically displays how the design
will be implemented on the chip. It provides a view of the entire
device to show what memory elements and logic clusters have
been used for what part of the design. This gives the designer
an idea of what resources are free. The Architecture Explorer
allows you to zoom-in multiple times. At maximum zoom it
displays the logic gate implementation in each macrocell. The
Architecture Explorer is available for PSI and Delta39K
devices.
Figure 5. Three-Bit Shift Register Circuit Design
clk
d
q
clk
d
q
clk
d
q
x
clk
q0
q1
q2
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY3130 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Warp Enterprise⑩ VHDL CPLD Software |
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| CY3138R62 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Programmable Logic |
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