參數(shù)資料
型號: CY2PP3115
英文描述: Clocks and Buffers
中文描述: 時鐘和緩沖器
文件頁數(shù): 9/12頁
文件大?。?/td> 246K
代理商: CY2PP3115
PRELIMINARY
FastEdge Series
CY2PP3115
Document #: 38-07502 Rev.*A
Page 9 of 12
V T T
Z o = 5 0 o h m
5 "
V T T
R
T
= 5 0 o h m
5 "
C Y 2 P P 3 1 1 5
R
T
= 5 0 o h m
V C C
V E E
V B B
Figure 10. Driving a PECL/ECL Single-ended Input
C Y 2 P P 3 1 1 5
3 .3 V
Z o = 5 0 o h m
3 .3 V
5 "
5 "
1 2 0 o h m
1 2 0 o h m
V C C = 3 .3 V
V E E = 0 V
L V D S
5 1 o h m
(2 p la ce s)
3 3 o h m
(2 p la ce s)
L V P E C L to
L V D S
Figure 11. Low-voltage Positive Emitter-Coupled Logic (LVPECL) to a Lo
w-voltage Differential
Signaling (LVDS) Interface
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