
CY2907
Single-PLL General-Purpose
EPROM Programmable Clock Generator
Cypress Semiconductor Corporation
Document #: 38-07137 Rev. **
3901 North First Street
San Jose
CA 95134
Revised September 26, 2001
408-943-2600
Selector Guide
CyClocks is a trademark of Cypress Semiconductor Corporation.
Features
Benefits
Single phase-locked loop architecture
EPROM programmability
Factory-programmable (CY2907, CY2907I) or field-pro-
grammable (CY2907F & CY2907FI) device options
Up to two configurable outputs
Low-skew, low-jitter, high-accuracy outputs
Power management (Power-Down, OE)
Frequency select option
Configurable 5V or 3.3V operation
8-pin or 14-pin SOIC packages
Generates a custom frequency from an external source
Easy customization and fast turnaround
Programming support available for all opportunities
Provides clocking requirements from a single device
Meets critical industry standard timing requirements
Supports low-power applications
Up to 16 user-selectable frequencies
Supports industry-standard design platforms
Industry-standard packaging saves on board space
Part Number
CY2907
Outputs
2
Input Frequency Range
10 MHz
–
25 MHz (external crystal)
1 MHz
–
30 MHz (reference clock)
10 MHz
–
25 MHz (external crystal)
1 MHz
–
30 MHz (reference clock)
10 MHz
–
25 MHz (external crystal)
1 MHz
–
30 MHz (reference clock)
10 MHz
–
25 MHz (external crystal)
1 MHz
–
30 MHz (reference clock)
Output Frequency Range
500 kHz
–
130 MHz (5V)
500 kHz
–
100 MHz (3.3V)
500 kHz
–
100 MHz (5V)
500 kHz
–
80 MHz (3.3V)
500 kHz
–
100 MHz (5V)
500 kHz
–
80 MHz (3.3V)
500 kHz
–
90 MHz (5V)
500 kHz
–
66.66 MHz (3.3V)
Specifics
Factory Programmable
Commercial Temperature
Factory Programmable
Industrial Temperature
Field Programmable
Commercial Temperature
Field Programmable
Industrial Temperature
CY2907I
2
CY2907F8
CY2907F14
CY2907F8I
CY2907F14I
2
2
XTALOUT
XTALIN
REFCLK
OSC.
1
2
3
4
5
6
7
10
9
8
11
14
13
12
Top View
14-Pin SOIC
S1
S2
S3
V
SS
V
SS
PD
XTALIN
S0
REFCLK
V
DD
CLKA
OEA
OER
XTALOUT
CLKA
PLL
EPROM
Table
S0
S1
S2
S3
OER
Output
Multiplexer
and
Dividers
PD
1
2
3
4
5
8
7
6
S0
V
SS
XTALIN
XTALOUT
REFCLK
V
DD
CLKA
S1
8-Pin SOIC
Configuration
EPROM
and Test Logic
OEA
Logic Block Diagram
Pin Configurations