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參數(shù)資料
| 型號(hào)： | CY28508OXCT |
| 廠商： | Silicon Laboratories Inc |
| 文件頁(yè)數(shù)： | 12/13頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK SSCG 3DIFF PAIR 28SSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | * |
| PLL： | 是 |
| 輸入： | 晶體 |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:4 |
| 差分 - 輸入:輸出： | 無(wú)/是 |
| 頻率 - 最大： | 333.3MHz |
| 除法器/乘法器： | 是/無(wú) |
| 電源電壓： | 2.375 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | * |
| 封裝/外殼： | * |
| 供應(yīng)商設(shè)備封裝： | * |
| 包裝： | * |
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CY28508
........................ Document #: 38-07534 Rev. *F Page 8 of 13
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace
capacitance and pin capacitance must also be considered to
correctly calculate crystal loading. As mentioned previously,
the capacitance on each side of the crystal is in series with the
crystal. This means the total capacitance on each side of the
crystal must be twice the specified crystal load capacitance
(CL). While the capacitance on each side of the crystal is in
series with the crystal, trim capacitors (Ce1,Ce2) should be
calculated to provide equal capacitive loading on both sides.
As mentioned previously, the capacitance on each side of the
crystal is in series with the crystal. This mean the total capac-
itance on each side of the crystal must be twice the specified
load capacitance (CL). While the capacitance on each side of
the crystal is in series with the crystal, trim capacitors (Ce1,
Ce2) should be calculated to provide equal capacitive loading
on both sides.
Use the following formulas to calculate the trim capacitor
values for Ce1 and Ce2.
CL....................................................Crystal load capacitance
CLe......................................... Actual loading seen by crystal
using standard value trim capacitors
Ce..................................................... External trim capacitors
Cs ........................................... Stray capacitance (trace, etc.)
Ci ........... Internal capacitance (lead frame, bond wires, etc.)
CPU_STOP# Clarification
The CPU_STOP# signal is an active LOW input used for
synchronous stopping and starting of the CPU output clocks
while the rest of the clock generator continues to function. The
REF output is not affected by the CPU_STOP# signal.
CPU_STOP# Assertion
When CPU_STOP# pin is asserted, all CPUT/C outputs will be
stopped after being sampled by two rising edges of the CPUT
clocks. The final state of the stopped CPU signals is CPUT =
LOW and CPU0C = HIGH.
XTA L
Ce2
Ce1
Cs1
Cs2
X1
X2
Ci1
Ci2
Clock Chip
Trace
2.8pF
Trim
33pF
Pin
3 to 6p
Figure 3. Crystal Loading Example
Load Capacitance (each side)
Total Capacitance (as seen by the crystal)
Ce = 2 * CL - (Cs + Ci)
Ce1 + Cs1 + Ci1
1
+
Ce2 + Cs2 + Ci2
1
()
1
=
CLe
2.0V
V DD_ A L L
CP UT
CP UC
RE F
<1.2 m s ec
LO C K
Figure 4. Power-up Signal Timing
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