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參數(shù)資料
| 型號(hào)： | CY28446LFXC |
| 廠商： | Silicon Laboratories Inc |
| 文件頁(yè)數(shù)： | 19/19頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK CALISTOGA CK410M 64QFN |
| 標(biāo)準(zhǔn)包裝： | 260 |
| 類型： | 時(shí)鐘/頻率發(fā)生器 |
| PLL： | 是 |
| 主要目的： | Intel CPU 服務(wù)器 |
| 輸入： | LVTTL，晶體 |
| 輸出： | HCSL，LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 3:20 |
| 差分 - 輸入:輸出： | 無(wú)/是 |
| 頻率 - 最大： | 200MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 64-QFN（9x9） |
| 包裝： | 托盤 |
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CY28446
.......................Document #: 001-00168 Rev *F Page 9 of 19
is in series with the crystal. The total capacitance on both side
is twice the specified crystal load capacitance (CL). Trim
capacitors are calculated to provide equal capacitive loading
on both sides.
Use the following formulas to calculate the trim capacitor
values for Ce1 and Ce2.
CL....................................................Crystal load capacitance
CLe......................................... Actual loading seen by crystal
using standard value trim capacitors
Ce..................................................... External trim capacitors
Cs .............................................. Stray capacitance (terraced)
Ci ...........................................................Internal capacitance
(lead frame, bond wires etc.)
OE# Description
The OE# signals are active LOW inputs used for clean
enabling and disabling selected SRC outputs. The outputs
controlled by OE[A,B]# are determined by the settings in
register byte 3 and byte 8. OE[0,1,3,6]# controls SRC[0,1,3,6],
respectively. The OE# signal is a debounced signal and its
state must remain unchanged during two consecutive rising
edges of SRCC to be recognized as a valid assertion or
deassertion. (The assertion and deassertion of this signal is
absolutely asynchronous.)
OE# Assertion (OE# -> LOW)
All differential stopped outputs resume normal operation in a
glitch-free manner. The maximum latency from the assertion
to active outputs is between 2 and 6 SRC clock periods (2
clocks are shown) with all SRC outputs resuming simultane-
ously. All stopped SRC outputs must be driven HIGH within 10
ns of OE# deassertion to a voltage er than 200 mV.
OE# Deassertion (OE# -> HIGH)
The impact of deasserting the OE# pins is that all SRC outputs
that are set in the control registers to stoppable via deassertion
of OE# are stopped after their next transition. The final state
of all stopped SRC clocks is Low/low.
XTAL
Ce2
Ce1
Cs1
Cs2
X1
X2
Ci1
Ci2
Clock Chip
Trace
2.8 pF
Trim
33 pF
Pin
3 to 6p
Figure 2. Crystal Loading Example
Load Capacitance (each side)
Total Capacitance (as seen by the crystal)
Ce = 2 * CL – (Cs + Ci)
Ce1 + Cs1 + Ci1
1
+
Ce2 + Cs2 + Ci2
1
()
1
=
CLe
SRCT(stoppable)
SRCC(free running)
SRCT(free running)
OE#
Figure 3. OE# Deassertion/Assertion Waveform
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY28446LFXCT | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Calistoga RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| CY28447 | 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:Clock Generator for Intel㈢ Calistoga Chipset |
| CY28447LFXC | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Calistoga System Clk Extra SRC Output RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| CY28447LFXCT | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Calistoga System Clk Extra SRC Output RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| CY28506OC | 制造商:Rochester Electronics LLC 功能描述:FTG FOR MOTHERBOARDS - Bulk |
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