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參數(shù)資料
型號(hào)： CY28419OXCT
廠商： Silicon Laboratories Inc
文件頁數(shù)： 5/15頁
文件大?。?/td> 0K
描述： IC CLOCK SRC CK409B 56SSOP
標(biāo)準(zhǔn)包裝： 1,000
類型： *
PLL： 是
輸入： 晶體
輸出： 時(shí)鐘
電路數(shù)： 1
比率 - 輸入:輸出： 1:25
差分 - 輸入:輸出： 無/是
頻率 - 最大： 400MHz
除法器/乘法器： 是/無
電源電壓： 3.135 V ~ 3.465 V
工作溫度： 0°C ~ 70°C
安裝類型： *
封裝/外殼： *
供應(yīng)商設(shè)備封裝： *
包裝： *
CY28419
......................Document #: 38-07444 Rev. *D Page 13 of 15
PCI / PCIF
TDC
PCIF and PCI Duty Cycle
Measurement at 1.5V
45
55
%
TPERIOD
Spread Disabled PCIF/PCI Period Measurement at 1.5V
29.9910
30.0009
ns
TPERIOD
Spread Enabled PCIF/PCI Period
Measurement at 1.5V
29.9910
30.1598
ns
THIGH
PCIF and PCI High Time
Measurement at 2.0V
12.0
–
nS
TLOW
PCIF and PCI Low Time
Measurement at 0.8V
12.0
–
nS
TR / TF
PCIF and PCI rise and fall times
Measured between 0.8V and 2.0V
0.5
2.0
nS
TSKEW
Any PCI Clock to Any PCI Clock
Skew
Measurement at 1.5V
–
500
pS
TCCJ
PCIF and PCI Cycle-to-Cycle Jitter Measurement at 1.5V
–
250
ps
DOT
TDC
DOT Duty Cycle
Measurement at 1.5V
45
55
%
TPERIOD
DOT Period
Measurement at 1.5V
20.8257
20.8340
ns
THIGH
DOT High Time
Measurement at 2.0V
8.994
10.486
nS
TLOW
DOT Low Time
Measurement at 0.8V
8.794
10.386
nS
TR / TF
Rise and Fall Times
Measured between 0.8V and 2.0V
0.5
1.0
ns
TLTJ
Long-term Jitter
10-
s period
–
2.0
ns
USB
TDC
USB Duty Cycle
Measurement at 1.5V
45
55
%
TPERIOD
USB Period
Measurement at 1.5V
20.8257
20.8340
ns
THIGH
USB High Time
Measurement at 2.0V
8.094
10.036
nS
TLOW
USB Low Time
Measurement at 0.8V
7.694
9.836
nS
TR / TF
Rise and Fall Times
Measured between 0.8V and 2.0V
1.0
2.0
ns
TLTJ
Long-term Jitter
125-
s period
–
6.0
ns
REF
TDC
REF Duty Cycle
Measurement at 1.5V
45
55
%
TPERIOD
REF Period
Measurement at 1.5V
69.827
69.855
ns
TR / TF
REF Rise and Fall Times
Measured between 0.8V and 2.0V
1.0
4.0
V/ns
TCCJ
REF Cycle-to-Cycle Jitter
Measurement at 1.5V
–
1000
ps
ENABLE/DISABLE and SET-UP
TSTABLE
Clock Stabilization from Power-up
–
1.8
ms
TSS
Stopclock Set-up Time
10.0
–
ns
TSH
Stopclock Hold Time
0
–
ns
AC Electrical Specifications (continued)
Parameter
Description
Conditions
Min.
Max.
Unit
Table 7. Group Timing Relationship and Tolerances
Group
Conditions
Offset
Min.
Max.
3V66 to PCI
3V66 Leads PCI
1.5 ns
3.5 ns
Table 8. USB to DOT Phase Offset
Parameter
Typical
Value
Tolerance
DOT Skew
0°
0.0ns
1000 ps
USB Skew
180°
0.0ns
1000 ps
VCH SKew
0°
0.0ns
1000 ps
Table 9. Maximum Lumped Capacitive Output Loads
Clock
Max Load
Unit
PCI Clocks
30
pF
3V66 Clocks
30
pF
USB Clock
20
pF
DOT Clock
10
pF
REF Clock
30
pF
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