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CY28410
......................Document #: 38-07593 Rev. *C Page 10 of 17
Figure 4. Power-down Deassertion Timing Waveform
DOT96C
PD
CPUC, 133MHz
CPUT, 133MHz
SRCC 100MHz
USB, 48MHz
DOT96T
SRCT 100MHz
Tstable
<1.8nS
PCI, 33MHz
REF
Tdrive_PW RDN#
<300
S, >200mV
FS_A, FS_B,FS_C
VTT_PW RGD#
PW RGD_VRM
VDD Clock Gen
Clock State
Clock Outputs
Clock VCO
0.2-0.3m S
Delay
State 0
State 2
State 3
Wait for
VTT_PW RGD#
Sam ple Sels
Off
On
State 1
Dev ice is not affected,
VTT_PW RGD# is ignored
Figure 5. VTT_PWRGD# Timing Diagram
VTT_PW R G D# = Low
Delay
> 0.25m S
S1
Power O ff
S0
V D D _A = 2.0V
Sam ple
Inputs straps
S2
Norm al
O peration
W ait for <1.8m s
Enable O utputs
S3
VTT_PW RG D # = toggle
VD D_A = off
Figure 6. Clock Generator Power-up/Run State Diagram
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