- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9006 > CY28409ZXCT (Silicon Laboratories Inc)IC CLOCK CK409GRANTSDALE 56TSSOP PDF資料下載
參數(shù)資料
| 型號： | CY28409ZXCT |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 15/16頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK CK409GRANTSDALE 56TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 類型： | * |
| PLL： | 是 |
| 輸入： | 晶體 |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:21 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 400MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | * |
| 封裝/外殼： | * |
| 供應(yīng)商設(shè)備封裝： | * |
| 包裝： | * |
| 其它名稱： | SLCY28409ZXCT |
CY28409
........................Document #: 38-07445 Rev. *D Page 8 of 16
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace
capacitance and pin capacitance must also be considered to
correctly calculate crystal loading. As mentioned previously,
the capacitance on each side of the crystal is in series with the
crystal. This means the total capacitance on each side of the
crystal must be twice the specified crystal load capacitance
(CL). While the capacitance on each side of the crystal is in
series with the crystal, trim capacitors (Ce1,Ce2) should be
calculated to provide equal capacitive loading on both sides.
Use the following formulas to calculate the trim capacitor
values for Ce1 and Ce2.
CL....................................................Crystal load capacitance
CLe......................................... Actual loading seen by crystal
using standard value trim capacitors
Ce..................................................... External trim capacitors
Cs .............................................. Stray capacitance (terraced)
Ci ...........................................................Internal capacitance
(lead frame, bond wires etc.)
PD# (Power-down) Clarification
The PD# (Power-down) pin is used to shut off ALL clocks prior
to shutting off power to the device. PD# is an asynchronous
active LOW input. This signal is synchronized internally to the
device powering down the clock synthesizer. PD# is an
asynchronous function for powering up the system. When PD#
is LOW, all clocks are driven to a LOW value and held there
and the VCO and PLLs are also powered down. All clocks are
shut down in a synchronous manner so as not to cause
glitches while changing to the low ‘stopped’ state.
PD# Assertion
When PD# is sampled LOW by two consecutive rising edges
of the CPUC clock then all clock outputs (except CPU) clocks
must be held LOW on their next HIGH-to-LOW transition. CPU
clocks must be held with CPU clock pin driven HIGH with a
value of 2 x Iref and CPUC undriven. Due to the state of
internal logic, stopping and holding the REF clock outputs in
the LOW state may require more than one clock cycle to
complete
XTAL
Ce 2
Ce 1
Cs 1
Cs 2
X1
X2
Ci1
Ci2
Clo c k Ch ip
( C Y 28409)
Tr a c e
2. 8 p F
Tr im
33pF
Pin
3 t o 6p
Figure 2. Crystal Loading Example
Load Capacitance (each side)
Total Capacitance (as seen by the crystal)
Ce = 2 * CL – (Cs + Ci)
Ce1 + Cs1 + Ci1
1
+
Ce2 + Cs2 + Ci2
1
()
1
=
CLe
PD#
3V66, 66MHz
USB, 48MHz
PCI, 33MHz
REF
SRCT 100MHz
SRCC 100MHz
CPUC, 133MHz
CPUT, 133MHz
Figure 3. Power-down Assertion Timing Waveform
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VE-2NT-MW-F2 | CONVERTER MOD DC/DC 6.5V 100W |
| VE-B0R-MY-F4 | CONVERTER MOD DC/DC 7.5V 50W |
| VE-2NT-MW-F1 | CONVERTER MOD DC/DC 6.5V 100W |
| ICS810525AGILFT | IC VCXO-LVCMOS/LVTTL 16-TSSOP |
| AD5623RBCPZ-3REEL7 | IC DAC NANO 12BIT DUAL 10-LFCSP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY28410 | 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:Clock Generator for Intel Grantsdale Chipset |
| CY28410-2 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Clock Generator for Intel Grantsdale Chipset |
| CY284108OXC | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Server, CK410B RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| CY284108OXCT | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Server, CK410B RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| CY284108ZXC | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Server, CK410B RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。