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| 型號(hào)： | CY28341-3 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時(shí)鐘和緩沖器 |
| 文件頁(yè)數(shù)： | 5/17頁(yè) |
| 文件大?。?/td> | 240K |
| 代理商： | CY28341-3 |
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CY28312B-2
Document #: 38-07596 Rev. **
Page 5 of 17
CY28312B-2 Serial Configuration Map
The serial bits will be read by the clock driver in the following
order:
Byte 0–Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1–Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte N–Bits 7, 6, 5, 4, 3, 2, 1, 0
All unused register bits (reserved and N/A) should be written
to a “0” level.
All register bits labeled “Initialize to 0” must be written to zero
during initialization.
29
Acknowledge from slave
Data byte from slave – 8 bits
Not Acknowledge
Stop
30:37
38
39
Table 3. Byte Read and Byte Write Protocol
(continued)
Byte Write Protocol
Byte Read Protocol
Bit
Description
Bit
Description
Byte 0: Control Register 0
Bit
Pin#
–
Name
Default
0
Description
Bit 7
Spread Enable
0 = Disabled
1 = Enabled
‘000’ = ±0.25%
‘001’ = –0.5%
‘010’ = ±0.5%
‘011’ = ±0.38%
‘100’ = Reserved
‘101’ = Reserved
‘110’ = Reserved
‘111’ = Reserved
SW Frequency selection bits. See
Table 4
.
Bit 6
Bit 5
Bit 4
–
–
–
Spread Select2
Spread Select1
Spread Select0
0
0
0
Bit 3
Bit 2
Bit 1
Bit 0
–
–
–
–
SEL3
SEL2
SEL1
SEL0
0
0
0
0
Byte 1: Control Register 1
Bit
Pin#
42, 41
39, 38
Name
Default
1
1
Description
Bit 7
Bit 6
CPUT0, CPUC0
CPUT_CS,
CPUC_CS
48MHz
24_48MHz
Reserved
AGP2
AGP1
AGP0
(Active/Inactive)
(Active/Inactive)
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
6
7
–
28
27
26
1
1
0
1
1
1
(Active/Inactive)
(Active/Inactive)
Reserved
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Byte 2: Control Register 2
Bit
Pin#
20
18
17
16
14
Name
Default
1
1
1
1
1
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
PCI7
PCI6
PCI5
PCI4
PCI3
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY28341OC | 制造商:Rochester Electronics LLC 功能描述:FTG FOR VIA P4 CHIPSET - Bulk |
| CY28341OC-2 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY28341OC-2T | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Universal Clock Chip for VIA⑩P4M/KT/KM400 DDR Systems |
| CY28341OC-3 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Universal Clock Chip for VIA⑩P4M/KT/KM400A DDR Systems |
| CY28341OC-3T | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
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