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參數資料
| 型號： | CY28325-2 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數： | 15/17頁 |
| 文件大?。?/td> | 240K |
| 代理商： | CY28325-2 |
CY28312B-2
Document #: 38-07596 Rev. **
Page 15 of 17
t
SK
f
ST
Output Skew
Frequency Stabilization
from Power-up (cold start)
AC Output Impedance
Measured on rising edge at 1.5V
Assumes full supply voltage reached within 1 ms from
power-up. Short cycles exist prior to frequency stabilization.
Average value during switching transition. Used for
determining series termination value.
300
3
ps
ms
Z
o
30
REF Clock Outputs (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
Frequency generated by crystal oscillator
Measured from 0.8V to 2.0V
Measured from 2.0V to 0.8V
Measured on rising and falling edge at 1.5V
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to
frequency stabilization.
Average value during switching transition. Used
for determining series termination value.
Min.
Typ.
14.318
Max.
Unit
MHz
V/ns
V/ns
%
ms
f
t
R
t
F
t
D
f
ST
Frequency, Actual
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Frequency Stabilization from
Power-up (cold start)
0.5
0.5
45
2
2
55
3
Z
o
AC Output Impedance
40
48-MHz Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
Determined by PLL divider ratio (see m/n below)
(48.008 – 48)/48
(14.31818 MHz x 57/17 = 48.008 MHz)
Measured from 0.8V to 2.0V
Measured from 2.0V to 0.8V
Measured on rising and falling edge at 1.5V
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to
frequency stabilization.
Average value during switching transition. Used
for determining series termination value.
Min.
Typ.
48.008
+167
57/17
Max.
Unit
MHz
ppm
f
f
D
m/n
t
R
t
F
t
D
f
ST
Frequency, Actual
Deviation from 48 MHz
PLL Ratio
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Frequency Stabilization
from Power-up (cold start)
0.5
0.5
45
2
2
55
3
V/ns
V/ns
%
ms
Z
o
AC Output Impedance
40
24-MHz Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
Determined by PLL divider ratio (see m/n below)
(24.004 – 24)/24
(14.31818 MHz x 57/34 = 24.004 MHz)
Measured from 0.8V to 2.0V
Measured from 2.0V to 0.8V
Measured on rising and falling edge at 1.5V
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to
frequency stabilization.
Average value during switching transition. Used
for determining series termination value.
Min.
Typ.
24.004
+167
57/34
Max.
Unit
MHz
ppm
f
f
D
m/n
t
R
t
F
t
D
f
ST
Frequency, Actual
Deviation from 24 MHz
PLL Ratio
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Frequency Stabilization
from Power-up (cold start)
0.5
0.5
45
2
2
55
3
V/ns
V/ns
%
ms
Z
o
AC Output Impedance
40
AGP Clock Outputs (Lump Capacitance Test Load = 30 pF)
(continued)
Parameter
Description
Test Condition/Comments
Min.
Typ.
Max.
Unit
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相關代理商/技術參數 |
參數描述 |
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| CY28325OC-3T | 制造商:Rochester Electronics LLC 功能描述:FTG FOR INTEL P4,VIA CHIPSETS - Bulk |
| CY28325OXC-3 | 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:FTG for VIA⑩ Pentium 4⑩ Chipsets |
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