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參數(shù)資料
| 型號(hào)： | CY28323 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時(shí)鐘和緩沖器 |
| 文件頁數(shù)： | 7/17頁 |
| 文件大?。?/td> | 240K |
| 代理商： | CY28323 |
CY28312B-2
Document #: 38-07596 Rev. **
Page 7 of 17
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Reserved
1
1
1
1
Reserved
Reserved
Reserved
Reserved
Byte 7: Reserved Register
Bit
Name
Default
1
1
1
1
1
1
1
1
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Byte 8: Vendor ID and Revision ID Register (Read-only)
Bit
Name
Default
0
0
0
0
1
0
0
0
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Revision_ID3
Revision_ID2
Revision_ID1
Revision_ID0
Vendor_ID3
Vendor_ID2
Vendor _ID1
Vendor _ID0
Revision ID bit[3]
Revision ID bit[2]
Revision ID bit[1]
Revision ID bit[0]
Bit[3] of Cypress’s Vendor ID. This bit is read-only.
Bit[2] of Cypress’s Vendor ID. This bit is read-only.
Bit[1] of Cypress’s Vendor ID. This bit is read-only.
Bit[0] of Cypress’s Vendor ID. This bit is read-only.
Byte 9: System Reset and Watchdog Timer Register
Bit
Name
Default
0
0
Description
Bit 7
Bit 6
Reserved
PCI_DRV
Reserved
PCI clock output drive strength
0 = Normal
1 = High Drive
Reserved
This bit will enable the generation of a Reset pulse when a Watchdog timer time-out
occurs.
0 = Disabled
1 = Enabled
This bit will enable the generation of a Reset pulse after a frequency change occurs.
0 = Disabled
1 = Enabled
Watchdog Timer Time-out Status bit
0 = No time-out occurs (READ); Ignore (WRITE)
1 = time-out occurred (READ); Clear WD_TO_STATUS (WRITE)
0 = Stop and reload Watchdog timer
1 = Enable Watchdog timer. It will start counting down after a frequency change occurs.
Reserved
Bit 5
Bit 4
Reserved
RST_EN_WD
0
0
Bit 3
RST_EN_FC
0
Bit 2
WD_TO_STATUS
0
Bit 1
WD_EN
0
Bit 0
Reserved
0
Byte 6: Reserved Register
(continued)
Bit
Name
Default
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY28325-2 | Clocks and Buffers |
| CY28330 | Clocks and Buffers |
| CY28331 | Clocks and Buffers |
| CY28331-2 | Clocks and Buffers |
| CY28341-3 | Clocks and Buffers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY28323B | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:FTG for Intel Pentium 4 CPU and Chipsets |
| CY28323BPVC | 制造商:Cypress Semiconductor 功能描述: |
| CY28323BPVCT | 制造商:Cypress Semiconductor 功能描述:Programmable PLL Frequency Generator Dual 48-Pin SSOP T/R |
| CY28323OXC | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Brookdale RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| CY28323OXCT | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Brookdale RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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