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參數(shù)資料
| 型號： | CY28317 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數(shù)： | 8/17頁 |
| 文件大?。?/td> | 240K |
| 代理商： | CY28317 |
CY28312B-2
Document #: 38-07596 Rev. **
Page 8 of 17
Byte 10: Skew Control Register
Bit
Name
Default
0
0
0
Description
Bit 7
Bit 6
Bit 5
CPU_Skew2
CPU_Skew1
CPU_Skew0
CPU skew control
000 = Normal
001 = –150 ps
010 = –300 ps
011 = –450 ps
100 = +150 ps
101 = +300 ps
110 = +450 ps
111 = +600 ps
Reserved
PCI skew control
00 = Normal
01 = –500 ps
10 = Reserved
11 = +500 ps
AGP skew control
00 = Normal
01 = –150 ps
10 = +150 ps
11 = +300 ps
Bit 4
Bit 3
Bit 2
Reserved
PCI_Skew1
PCI_Skew0
0
0
0
Bit 1
Bit 0
AGP_Skew1
AGP_Skew0
0
0
Byte 11: Recovery Frequency N–Value Register
Bit
Name
Default
0
0
0
0
0
0
0
0
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ROCV_FREQ_N7
ROCV_FREQ_N6
ROCV_FREQ_N5
ROCV_FREQ_N4
ROCV_FREQ_N3
ROCV_FREQ_N2
ROCV_FREQ_N1
ROCV_FREQ_N0
If ROCV_FREQ_SEL is set, CY28312B-2 will use the values programmed in
ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] to determine the recovery
CPU output frequency.when a Watchdog timer time-out occurs.
The setting of FS_Override bit determines the frequency ratio for CPU,
SDRAM, AGP and SDRAM. When it is cleared, CY28312B-2 will use the same
frequency ratio stated in the Latched FS[4:0] register. When it is set,
CY28312B-2 will use the frequency ratio stated in the SEL[4:0] register.
CY28312B-2 supports programmable CPU frequency ranging from 50 MHz to
248 MHz.
CY28312B-2 will change the output frequency whenever there is an update to
either ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0]. Therefore, it is recom-
mended to use Word or Block write to update both registers within the same
SMBus bus operation.
Byte 12: Recovery Frequency M–Value Register
Bit
Name
Default
0
Pin Description
Bit 7
ROCV_FREQ_SEL
ROCV_FREQ_SEL determines the source of the recover frequency when a
Watchdog timer time-out occurs. The clock generator will automatically switch
to the recovery CPU frequency based on the selection on ROCV_FREQ_SEL.
0 = From latched FS[4:0]
1 = From the settings of ROCV_FREQ_N[7:0] & ROCV_FREQ_M[6:0]
If ROCV_FREQ_SEL is set, CY28312B-2 will use the values programmed in
ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] to determine the recovery
CPU output frequency.when a Watchdog timer time-out occurs
The setting of FS_Override bit determines the frequency ratio for CPU,
SDRAM, AGP and SDRAM. When it is cleared, CY28312B-2 will use the same
frequency ratio stated in the Latched FS[4:0] register. When it is set,
CY28312B-2 will use the frequency ratio stated in the SEL[4:0] register.
CY28312B-2 supports programmable CPU frequency ranging from 50 MHz to
248 MHz.
CY28312B-2 will change the output frequency whenever there is an update to
either ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0]. Therefore, it is recom-
mended to use Word or Block write to update both registers within the same
SMBus bus operation.
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ROCV_FREQ_M6
ROCV_FREQ_M5
ROCV_FREQ_M4
ROCV_FREQ_M3
ROCV_FREQ_M2
ROCV_FREQ_M1
ROCV_FREQ_M0
0
0
0
0
0
0
0
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY28317-2 | 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:FTG for Mobile VIA⑩ PL133T and PLE133T Chipsets |
| CY28317PVC-2 | 制造商:Cypress Semiconductor 功能描述: |
| CY28317PVC-2T | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:FTG for Mobile VIA PL133T and PLE133T Chipsets |
| CY28317PVXC-2 | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 NB Clk VIA SDRAM Chipsets / Tualatin RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| CY28317PVXC-2T | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 NB Clk VIA SDRAM Chipsets / Tualatin RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
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