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參數(shù)資料
| 型號(hào)： | CY27EE16ZE |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | CAT5E PATCH CORD 100MHZ 5 FOOT BEIGE |
| 中文描述： | 1鎖相環(huán)在系統(tǒng)可編程時(shí)鐘發(fā)生器與個(gè)人16K的EEPROM的 |
| 文件頁數(shù)： | 11/17頁 |
| 文件大?。?/td> | 163K |
| 代理商： | CY27EE16ZE |
CY27EE16ZE
Document #: 38-07440 Rev. *B
Page 11 of 17
Sequential Read
Sequential read operations follow the same process as
random reads except that the master issues an acknowledge
instead of a STOP condition after transmission of the first 8-bit
data word. This action results in an incrementing of the internal
address pointer, and subsequently output of the next 8-bit data
word. By continuing to issue acknowledges instead of STOP
conditions, the master may serially read the entire contents of
the 16-kbit EEPROM scratchpad memory. When the internal
address pointer points to the FFH word of a EEPROM block,
after the next increment, the pointer will point to the 00H word
of the next block. After incrementing to the FFH word of the
eighth block, the next increment will point the pointer to the
00H word of the 1st EEPROM block. Similarly, sequential
reads within either the EEPROM or SRAM clock configuration
blocks will wrap within the block to the first word of the same
block after reaching the end of either block.
SCL
START
Condition
SDAT
STOP
Condition
Data may
be changed
Address or
Acknowledge
Valid
Figure 3. Data Transfer Sequence on the Serial Bus
SDAT Write
Multiple
Contiguous
Registers
Start Signal
Device
Address
7-bit
R/W = 0
1 Bit
8-bit
Register
Address
(XXH)
Slave
ACK
1 Bit
Slave
ACK
1 Bit
8-bit
Register
Data
(XXH)
Stop Signal
Slave
ACK
1 Bit
8-bit
Register
Data
(XXH+1)
Slave
ACK
1 Bit
8-bit
Register
Data
(XXH+2)
Slave
ACK
1 Bit
8-bit
Register
Data
(XXH)
Slave
ACK
1 Bit
8-bit
Register
Data
(X0H)
Slave
ACK
1 Bit
Slave
ACK
1 Bit
SDAT Read
Start Signal
Device
Address
7-bit
R/W = 1
1 Bit
8-bit
Register
Data
1 Bit
ACK
Slave
ACK
1 Bit
Stop Signal
SDAT Read
Multiple
Contiguous
Registers
Start Signal
Device
Address
7-bit
R/W = 0
1 Bit
8-bit
Register
Address
(XXH)
Slave
ACK
1 Bit
Slave
ACK
1 Bit
7-bit
Device
Address
+R/W=1
Stop Signal
Master
ACK
1 Bit
8-bit
Register
Data
(XXH)
Master
ACK
1 Bit
Master
ACK
1 Bit
8-bit
Register
Data
(XXH+1)
Master
ACK
1 Bit
8-bit
Register
Data
(8FFH)
Master
ACK
1 Bit
8-bit
Register
Data
(000H)
Master
ACK
1 Bit
Master
ACK
1 Bit
Current
Address
Read
16 byte wrap
Repeated
Start bit
Figure 4. Data Frame Architecture
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| CY27EE16FZEC | 1 PLL In-System Programmable Clock Generator with Individual 16K EEPROM |
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| CY27EE16ZE_04 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1 PLL In-System Programmable Clock Generator with Individual 16K EEPROM |
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| CY27EE16ZEC-300 | 制造商:Cypress Semiconductor 功能描述: |
| CY27EE16ZEC-XXX | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1 PLL In-System Programmable Clock Generator with Individual 16K EEPROM |
| CY27EE16ZEC-XXXT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1 PLL In-System Programmable Clock Generator with Individual 16K EEPROM |
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