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參數(shù)資料
| 型號： | CY27EE16FZEI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | 1 PLL In-System Programmable Clock Generator with Individual 16K EEPROM |
| 中文描述： | 167 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| 封裝： | 4.40 MM, EXPOSED PAD, TSSOP-20 |
| 文件頁數(shù)： | 12/17頁 |
| 文件大小： | 163K |
| 代理商： | CY27EE16FZEI |
CY27EE16ZE
Document #: 38-07440 Rev. *B
Page 12 of 17
Serial Programming Interface Timing
Thermal Land Pad on PWB: Layout
Requirement for 20-lead Exposed Pad TSSOP
In order to achieve power dissipation and maintain junction
temperature within specified limits there must be an exposed
landing pad placed under the package, and the exposed pad
on the bottom of the package must be soldered to this landing
pad. This is typically achieved by placing a dense array of
thermal via that connects the landing pad to the ground plane.
In order to meet the power dissipation specification of 40 °C/W,
Amkor soldered the exposed pad to a thermal land pad, and
placed thermal via on a 1.2-mm pitch (x and y) in the thermal
land pad. For more information about this package, see,
“Application Notes for Surface Mount Assembly of Amkor’s
Thermally/Electrically
Enhanced
Packages.” Amkor Technology, December 2001.
Leadframe
Based
SDAT
SCLK
Data Valid
Transition
to next Bit
CLK
LOW
CLK
HIGH
VIH
VIL
t
SU
t
DH
Figure 5. Data Valid and Data Transition Periods
Figure 6. Start and Stop Frame
Figure 7. Frame Format (Device Address, R/W, Register Address, Register Data)
SDAT
SCLK
START
Transition
to next Bit
STOP
SDAT
SCLK
DA6
DA5 DA0
+
R/W
ACK
RA7
RA6 RA1
+
RA0
ACK
STOP
START
ACK
D7
D6
D1
D0
+
+
+
+
Table 15. Pullable Crystal Specifications
Parameter
CRYSTAL
Load
C0/C1
ESR
T
o
T
o
Acc
init
Stability
Description
Min.
Typ.
14
Max.
Unit
pF
Load Capacitance
240
35
70
85
W
°C
°C
ppm
ppm
Operating Temperature (Commercial)
Operating Temperature (Industrial)
Initial Accuracy
Temperature plus Aging Stability
0
–40
±30
±80
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| CY27EE16FZEIT | 1 PLL In-System Programmable Clock Generator with Individual 16K EEPROM |
| CY27EE16ZEC | 1 PLL In-System Programmable Clock Generator with Individual 16K EEPROM |
| CY27EE16ZEI | 1 PLL In-System Programmable Clock Generator with Individual 16K EEPROM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY27EE16FZEIT | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1 PLL In-System Programmable Clock Generator with Individual 16K EEPROM |
| CY27EE16FZXEC | 制造商:Cypress Semiconductor 功能描述:Programmable PLL Clock Generator Single 20-Pin TSSOP |
| CY27EE16FZXECT | 制造商:Cypress Semiconductor 功能描述: |
| CY27EE16ZE | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1 PLL In-System Programmable Clock Generator with Individual 16K EEPROM |
| CY27EE16ZE_04 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:1 PLL In-System Programmable Clock Generator with Individual 16K EEPROM |
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