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參數(shù)資料
| 型號： | CY27EE16FZECT |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | 1 PLL In-System Programmable Clock Generator with Individual 16K EEPROM |
| 中文描述： | 200 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| 封裝： | 4.40 MM, EXPOSED PAD, TSSOP-20 |
| 文件頁數(shù)： | 14/17頁 |
| 文件大?。?/td> | 163K |
| 代理商： | CY27EE16FZECT |
CY27EE16ZE
Document #: 38-07440 Rev. *B
Page 14 of 17
AC Electrical Specifications (VDD = 3.3V)
Parameter
[5]
DC
Name
Description
Min.
45
40
Typ.
50
50
Max.
55
60
Unit
%
Clock Output Duty Cycle
f
OUT
< 150 MHz
f
OUT
> 150 MHz, or f
OUT
= f
REF
See
Figure 8
Output Clock Edge Rate, Measured from 20%
to 80% of V
DD,
C
LOAD
= 15 pF See
Figure 9
.
Output Clock Edge Rate, Measured from 80%
to 20% of V
DD,
C
LOAD
= 15 pF See
Figure 9
.
For related clock outputs
Maximum absolute jitter (EEPROM quiet)
(during EEPROM reads)
(during EEPROM writes)
ER
O
Rising Edge Rate
0.8
1.4
V/ns
EF
O
Falling Edge Rate
0.8
1.4
V/ns
t
5
t
9
Output to Output Skew
Clock Jitter
250
ps
ps
250
300
350
t
10
t
VDDramp
t
VDDpowerdown
PLL Lock Time
Power Supply Ramp
Power Supply Power
Down after Write
60
15
ms
ms
ms
Ramp time from 1.5V to 2.5V
[6]
Wait time after a write to EEPROM is initiated
by the stop bit until V
DD
fails below 2.5V
20
Memory Section Specifications
F
SCL
SCL input frequency
t
L
Clock Pulse Low
t
H
Clock Pulse High
t
SP
Noise Suppression Time
t
AA
Clock Low to Data Out
Valid
t
BUFF
Time the bus must be free
before a new transmission
may start
t
HDSTART
Start Hold Time
t
SUSTART
Start Set-up Time
t
DH
Data in Hold Time
t
SU
Data in Set-up time
t
RI
Inputs rise time
t
FI
Inputs fall time
t
SUSTOP
Stop Set-up Time
t
DH
Data Out Hold Time
t
WR
Write Cycle Time
400
1.2
kHz
μ
s
μ
s
ns
μ
s
CLK
LOW
, 20–80% of V
DD
CLK
HIGH
, 80–20% of V
DD
Square noise spike on input
0.6
50
0.9
0.1
1.2
μ
s
0.6
0.6
0
100
μ
s
μ
s
ms
ns
ns
ns
μ
s
ns
ms
300
300
0.6
50
20
Test and Measurement Set-up
Notes:
5.Not 100% tested.
6.The power supply voltage must increase monotonically from 0 to 2.5V; once V
DD
reaches 1.5V, it must ramp to 2.5V within 15 ms.
0.1
μ
F
V
DD
CLK out
C
LOAD
GND
OUTPUTS
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