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參數(shù)資料
| 型號： | CY27EE16FZEC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | 1 PLL In-System Programmable Clock Generator with Individual 16K EEPROM |
| 中文描述： | 200 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| 封裝： | 4.40 MM, EXPOSED PAD, TSSOP-20 |
| 文件頁數(shù)： | 5/17頁 |
| 文件大?。?/td> | 163K |
| 代理商： | CY27EE16FZEC |
CY27EE16ZE
Document #: 38-07440 Rev. *B
Page 5 of 17
Reference Frequency (REF)
The reference frequency can be a crystal or a driven
frequency. For crystals, the frequency range must be between
8 MHz and 30 MHz. For a driven frequency, the frequency
range must be between 1 MHz and 167 MHz (Commercial
Temp.) or 150 MHz (Industrial Temp.).
Using a Crystal as the Reference Input
The input crystal oscillator of the CY27EE16ZE is an important
feature because of the flexibility it allows the user in selecting
a crystal as a reference frequency source. The input oscillator
has programmable gain, allowing for maximum compatibility
with a reference crystal, regardless of manufacturer, process,
performance and quality.
Programmable Crystal Input Oscillator Gain Settings
The Input crystal oscillator gain (XDRV) is controlled by two
bits in register 12H, and are set according to
Table 3
. The
parameters controlling the gain are the crystal frequency, the
internal crystal parasitic resistance (ESR, available from the
manufacturer), and the CapLoad setting during crystal
start-up.
Bits 3 and 4 of register 12H control the input crystal oscillator
gain setting. Bit 4 is the MSB of the setting, and bit 3 is the
LSB. The setting is programmed according to
Table 3
.
All other bits in the register are reserved and should be
programmed LOW. See
Table 4
for bit locations and values.
(
Q+2)
[42H]
VCO
(2(PB+4)+PO)
[40H], [41H], [42H]
/2
/
3
/
2
CLOCK1
CLOCK2
CLOCK3
CLOCK4
CLOCK5
CLOCK6
CLKSRC
Crosspoint
Switch Matrix
[44H]
[44H]
[44H,45H]
[45H]
[46H]
D
REF
PFD
Divider Bank 1
[45H,46h]
DIV1SRC [OCH]
/
4
DIV2SRC [47H]
DIV2N [47H]
Divider Bank 2
DIV1N [OCH]
D
/DIV1N
1
0
1
0
/DIV2N
Q
total
P
total
CLKOE [09H]
Figure 2. Basic Block Diagram of CY27EE16ZE PLL
Table 3. Programmable Crystal Input Oscillator Gain Settings
Calculated CapLoad Value
Crystal ESR
8 – 15 MHz
15 – 20 MHz
20 – 25 MHz
25 – 30 MHz
00H – 20H
30
00
01
01
10
20H – 30H
30
01
01
10
10
30H – 40H
30
01
10
10
11
60
01
10
10
10
60
10
10
10
11
60
10
10
11
N/A
Crystal Input
Frequency
Table 4. Register Map for Input Crystal Oscillator Gain Setting
Address
12H
D7
D6
D5
D4
D3
D2
0
D1
0
D0
0
FTAAddrSrc(1)
default=0
FTAAddrSrc(0)
default=0
XCapSrc
default=1
XDRV(1)
XDRV(0)
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