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參數(shù)資料
| 型號： | CY26502 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數(shù)： | 6/13頁 |
| 文件大小： | 161K |
| 代理商： | CY26502 |
CY26501/CY26502
Document #: 38-07356 Rev. *A
Page 6 of 13
The control signals Mult0 and Mult1 can be used in two ways.
If they are changed during Power-down mode, then the Pow-
er-down transition timings determine the settling time of the
DRCG. However, the Mult0 and Mult1 control signals can also
be changed during Normal mode. When the Mult control sig-
nals are
“
hot swapped
”
in this manner, the Mult transition tim-
ings determine the settling time of the DRCG.
In Clock Stop mode, the clock source is on, but the output is
disabled (StopB asserted). The V
DDPD
reference input may
remain on or may be grounded during the Clk Stop mode. The
V
DDR
reference input must remain on during the Clock Stop
mode.
In Normal mode, the clock source is on, and the output is en-
abled.
Table 7
lists the control signals for each state.
Figure 5
shows the timing diagrams for the various transitions
between states, and
Table 8
specifies the latencies of each
state transition. Note that these transition latencies assume
the following:
Refclk input has settled and meets specification shown in
Table 13
.
Mult0, Mult1, S0 and S1 control signals are stable.
Table 7. Control Signals for Clock Source States
State
PwrDnB
0
1
1
StopB
X
0
1
Clock
Source
OFF
ON
ON
Output
Buffer
Ground
Disabled
Enabled
Power-down
Clock Stop
Normal
Timing Diagrams
s
Figure 5. State Transition Timing Diagram
Figure 6. Multiply Transition Timing
t
POWERUP
t
POWERDN
t
STOP
t
ON
t
CLKON
t
CLKOFF
t
CLKSETL
PwrDnB
Clk/ClkB
Power-Down Exit and Entry
Output Enable Control
StopB
Clk/ClkB
Output clock
not specified
glitches may
occur
Clock enabled
and glitch free
Clock output settled within
50 ps of the phase before
disabled
t
MULT
Clk/ClkB
Mult0 and/or Mult1
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