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參數(shù)資料
| 型號： | CY26210 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數(shù)： | 3/5頁 |
| 文件大小： | 87K |
| 代理商： | CY26210 |
PRELIMINARY
CY26200
Document #: 38-07335 Rev. *A
Page 3 of 5
Test Circuit
t
4
t
9
t
10
Falling Edge Slew Rate
Clock Jitter
PLL Lock Time
Output Clock Fall Time, 80% - 20% of V
DD
Peak to Peak period jitter
0.8
1.4
200
V/ns
ps
ms
3
AC Electrical Characteristics
(V
DD
= 3.3V, Industrial)
Parameter
[3]
Name
DC
Output Duty Cycle
t
3
Rising Edge Slew Rate
t
4
Falling Edge Slew Rate
t
9
Clock Jitter
t
10
PLL Lock Time
Description
Min.
45
0.8
0.8
Typ.
50
1.4
1.4
200
Max.
55
Unit
%
V/ns
V/ns
ps
ms
Duty Cycle is defined in
Figure 1
, 50% of V
DD
Output Clock Rise Time, 20%
–
80% of V
DD
Output Clock Fall Time, 80%
–
20% of V
DD
Peak to Peak period jitter
3
AC Electrical Characteristics
(V
DD
= 3.3V, Commercial) (continued)
Parameter
[3]
Description
Conditions
Min.
Typ.
Max.
Unit
Ordering Information
Ordering Code
CY26200SC
CY26200SI
Package Name
S8
S8
Package Type
8-lead SOIC
8-lead SOIC
Operating Range
Commercial
Industrial
Operating Voltage
3.3V
3.3V
0.1 mF
VDD
CLK out
CLOAD
GND
OUTPUTS
t1
t2
CLK
50%
50%
Figure 1. Duty Cycle Definition; DC = t2/t1
t3
CLK
80%
20%
t4
Figure 2. Rise and Fall Time Definitions
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