參數(shù)資料
型號(hào)： CY25822-2
英文描述： Clocks and Buffers
中文描述： 時(shí)鐘和緩沖器
文件頁(yè)數(shù)： 5/10頁(yè)
文件大?。?/td> 208K
代理商： CY25822-2
CY25811/12/14
Document #: 38-07112 Rev. *D
Page 5 of 10
AC Electrical Specifications
(Commercial Grade)
Parameter
F
IN
T
R1
T
F1
T
R2
T
F2
T
DCIN
T
DCOUT
T
CCJ1
T
CCJ2
T
CCJ3
T
CCJ4
T
CCJ5
T
CCJ6
T
SU
Description
Condition
Min.
4
2.0
2.0
1.0
1.0
40
40
–
–
–
–
–
–
–
Max.
32
5.0
4.4
2.2
2.2
60
60
800
450
400
380
380
380
3
Unit
MHz
ns
ns
ns
ns
%
%
ps
ps
ps
ps
ps
ps
ms
Input Frequency Range
Clock Rise Time
Clock Fall Time
Clock Rise Time
Clock Fall Time
Input Clock Duty Cycle
Output Clock Duty Cycle
Cycle-to-Cycle Jitter, Spread on
Cycle-to-Cycle Jitter, Spread on
Cycle-to-Cycle Jitter, Spread on
Cycle-to-Cycle Jitter, Spread on
Cycle-to-Cycle Jitter, Spread on
Cycle-to-Cycle Jitter, Spread on
PLL Lock Time
Clock, Crystal or Ceramic Resonator Input
SSCLK, CY25811 and CY25812
SSCLK, CY25811 and CY25812
SSCLK, only CY25814 when FRSEL = M
SSCLK, only CY25814 when FRSEL = M
XIN
SSCLK
Fin = 4 MHz, Fout = 4 MHz, CY25811
Fin = 8 MHZ, Fout = 8 MHz, CY25811
Fin = 8 MHz, Fout = 16 MHz, CY25812
Fin = 16 MHz, Fout = 32 MHz, CY25812
Fin = 16 MHz, Fout = 64 MHz, CY25814
Fin = 32 MHz, Fout = 128 MHz, CY25814
Fom V
DD
3.0V to valid SSCLK
DC Electrical Specifications
(Industrial Grade)
Parameter
V
DD
V
IL
V
IM
V
IH
V
OL1
V
OL2
V
OH1
V
OH2
C
IN1
C
IN2
C
L
I
DD1
I
DD2
I
DD3
Description
Condition
Min.
3.135
0
0.40V
DD
0.85V
DD
–
–
2.4
2.0
6.0
3.5
–
–
–
–
Max.
3.465
0.13V
DD
0.60V
DD
V
DD
0.4
1.2
–
–
9.0
6.0
15
26
32
37
Unit
V
V
V
V
V
V
V
V
pF
pF
pF
mA
mA
mA
3.3 Operating Voltage
Input Low Voltage
Input Middle Voltage
Input High Voltage
Output Low Voltage
Output Low Voltage
Output High Voltage
Output High Voltage
Input Pin Capacitance
Input Pin Capacitance
Output Load Capacitor
Dynamic Supply Current
Dynamic Supply Current
Dynamic Supply Current
3.3 ± 5%
S0, S1 and FRSEL Inputs
S0, S1 and FRSEL Inputs
S0, S1 and FRSEL Inputs
I
OL
= 4 ma, SSCLK Output
I
OL
= 10 ma, SSCLK Output
I
OH
= 4 ma, SSCLK Output
I
OH
= 6 ma, SSCLK Output
XIN (Pin 1) and XOUT (Pin 8)
All Digital Inputs
SSCLK Output
Fin = 12 MHz, no load
Fin = 24 MHz, no load
Fin = 32 MHz, no load
AC Electrical Specifications
(Industrial Grade)
Parameter
F
IN
T
R1
T
F1
T
R2
T
F2
T
DCIN
T
DCOUT
T
CCJ1
T
CCJ2
T
CCJ3
T
SU
Description
Condition
Min.
4
2.0
2.0
1.0
1.0
40
40
–
–
–
–
Max.
32
5.0
4.4
2.2
2.2
60
60
650
400
400
4
Unit
MHz
ns
ns
ns
ns
%
%
ps
ps
ps
ms
Input Frequency Range
Clock Rise Time
Clock Fall Time
Clock Rise Time
Clock Fall Time
Input Clock Duty Cycle
Output Clock Duty Cycle
Cycle-to-Cycle Jitter, Spread on
Cycle-to-Cycle Jitter, Spread on
Cycle-to-Cycle Jitter, Spread on
PLL Lock Time
Clock, Crystal or Ceramic Resonator Input
SSCLK, CY25811 and CY25812
SSCLK, CY25811 and CY25812
SSCLK, only CY25814 when FRSEL = M
SSCLK, only CY25814 when FRSEL = M
XIN
SSCLK
Fin = 6MHz, CY25811/12/14
Fin = 12MHZ, CY25811/12/14
Fin = 24MHz, CY25811/12/14
From V
DD
3.0V to valid SSCLK
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