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參數(shù)資料
| 型號(hào)： | CY2509ZC-1 |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | RF/Coaxial Connector; RF Coax Type:UHF; Contact Termination:Solder; Body Style:Straight Bulkhead Receptacle RoHS Compliant: Yes |
| 中文描述： | 2509 SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24 |
| 封裝： | 4.40 MM, TSSOP-24 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大?。?/td> | 100K |
| 代理商： | CY2509ZC-1 |
Spread Aware, Ten/Eleven Output Zero Delay Buffer
CY2509/10
Cypress Semiconductor Corporation
Document #: 38-07230 Rev. *A
3901 North First Street
San Jose
CA 95134
Revised December 14, 2002
408-943-2600
9/10
Features
Spread Aware
TM
—designed to work with SSFTG refer-
ence signals
Well suited to both 100- and 133-MHz designs
Ten (CY2509) or eleven (CY2510) LVCMOS/LVTTL
outputs
Single output enable pin for CY2510 version, dual pins
on CY2509 devices allow shutting down a portion of the
outputs
3.3V power supply
On board 25
damping resistors
Available in 24-pin TSSOP package
Improved tracking skew, but narrower frequency sup-
port limit when compared to W132-09B/10B
Key Specifications
Operating Voltage: ................................................3.3V±10%
Operating Range: ........................40 MHz < f
OUT
< 140 MHz
Cycle-to-Cycle Jitter: ................................................<100 ps
Output to Output Skew: ............................................<100 ps
Phase Error Jitter: .....................................................<100 ps
Spread Aware is a trademark of Cypress Semiconductor Corporation.
Block Diagram
Pin Configurations
Q0
PLL
Q1
Q2
Q3
Q5
Q6
OE0:4
Q7
Q8
FBOUT
Q4
Q9
OE
OE5:8
Configuration of these blocks dependent upon specific option being used
FBIN
CLK
CLK
AVDD
VDD
Q9
Q8
GND
GND
Q7
Q6
Q5
VDD
FBIN
24
23
22
21
20
19
18
17
16
15
14
13
AGND
VDD
Q0
Q1
Q2
GND
GND
Q3
Q4
VDD
OE
FBOUT
1
2
3
4
5
6
7
8
9
10
11
12
C
CLK
AVDD
VDD
Q8
Q7
GND
GND
Q6
Q5
VDD
OE5:8
FBIN
24
23
22
21
20
19
18
17
16
15
14
13
AGND
VDD
Q0
Q1
Q2
GND
GND
Q3
Q4
VDD
OE0:4
FBOUT
1
2
3
4
5
6
7
8
9
10
11
12
C
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY2510 | Spread Aware, Ten/Eleven Output Zero Delay Buffer |
| CY2510ZC-1 | Spread Aware, Ten/Eleven Output Zero Delay Buffer |
| CY2509 | Spread Aware Ten/Eleven Output Zero Delay Buffer( 十/十一輸出零延遲緩沖器) |
| CY25560 | Spread Spectrum Clock Generator(擴(kuò)頻時(shí)鐘發(fā)生器) |
| CY25561 | Spread Spectrum Clock Generator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY2509ZC-1T | 制造商:Cypress Semiconductor 功能描述: |
| CY2509ZXC-1 | 功能描述:鎖相環(huán) - PLL Zero Delay Buffr COM RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY2509ZXC-1T | 功能描述:鎖相環(huán) - PLL Zero Delay Buffr COM RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY2510 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Spread Aware Ten/Eleven Output Zero Delay Buffer |
| CY25100 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Field- and Factory-Programmable Spread Spectrum Clock Generator for EMI Reduction |
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