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參數(shù)資料
| 型號： | CY23S05 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數(shù)： | 2/9頁 |
| 文件大?。?/td> | 169K |
| 代理商： | CY23S05 |
CY23S05
CY23S09
Document #: 38-07296 Rev. *B
Page 2 of 9
Zero Delay and Skew Control
All outputs should be uniformly loaded to achieve Zero Delay
between the input and output. Since the CLKOUT pin is the
internal feedback to the PLL, its relative loading can adjust the
input-output delay. This is shown in the above graph.
For applications requiring zero input-output delay, all outputs,
including CLKOUT, must be equally loaded. Even if CLKOUT
is not used, it must have a capacitive load equal to that on
other outputs, for obtaining zero input-output delay. If input to
output delay adjustments are required, use the above graph to
calculate loading differences between the CLKOUT pin and
other outputs.
For zero output-output skew, be sure to load all outputs
equally. For further information, refer to the application note
“
CY23S05 and CY23S09 as PCI and SDRAM Buffers.
”
Spread Aware
Many systems being designed now utilize a technology called
Spread Spectrum Frequency Timing Generation. Cypress has
been one of the pioneers of SSFTG development, and we
designed this product so as not to filter off the Spread
Spectrum feature of the Reference input, assuming it exists.
When a zero delay buffer is not designed to pass the SS
feature through, the result is a significant amount of tracking
skew which may cause problems in systems requiring
synchronization.
For more details on Spread Spectrum timing technology,
please see the Cypress application note entitled,
“
EMI
Suppression Techniques with Spread Spectrum Frequency
Timing Generator (SSFTG) ICs.
”
Select Input Decoding for CY23S09
S2
S1
CLOCK A1
–
A4
CLOCK B1
–
B4
CLKOUT
[1]
Output Source
PLL Shut-down
0
0
Three-state
Three-state
Driven
PLL
N
0
1
Driven
Three-state
Driven
PLL
N
1
0
Driven
Driven
Driven
Reference
Y
1
1
Driven
Driven
Driven
PLL
N
Note:
1.
This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and output.
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PDF描述 |
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| CY23S09 | Clocks and Buffers |
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| CY2411 | Clocks and Buffers |
| CY24115 | Clocks and Buffers |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY23S05SC-1 | 制造商:Cypress Semiconductor 功能描述: |
| CY23S05SC-1H | 制造商:Cypress Semiconductor 功能描述: 制造商:Rochester Electronics LLC 功能描述:ZERO DELAY BUFFER 3.3 V SPREAD AWARE - Bulk |
| CY23S05SC-1T | 功能描述:鎖相環(huán) - PLL Zero Delay Buffr COM RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY23S05SI-1 | 功能描述:鎖相環(huán) - PLL Zero Delay Buffr IND RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY23S05SI-1T | 功能描述:鎖相環(huán) - PLL Zero Delay Buffer Spread Aware RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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