參數(shù)資料
型號: CY2318BNZPVI-11
英文描述: EIGHTEEN DISTRIBUTED-OUTPUT CLOCK DRIVER|SSOP|48PIN|PLASTIC
中文描述: 十八分布式輸出時鐘驅(qū)動器| SSOP封裝| 48PIN |塑料
文件頁數(shù): 4/6頁
文件大?。?/td> 75K
代理商: CY2318BNZPVI-11
CY2310BNZ
Document #: 38-07260 Rev. *A
Page 4 of 6
Test Circuit
Application Information
Clock traces must be terminated with either series or parallel
termination, as they are normally done.
Summary
Surface mount, low-ESR ceramic capacitors should be
used for filtering. Typically, these capacitors have a value
of 0.1
μ
F. In some cases, smaller value capacitors may be
required.
The value of the series-terminating resistor satisfies the
following equation where Rtrace is the loaded characteristic
impedance of the trace, Rout is the output impedance of the
buffer (typically 25W), and Rseries is the series terminating
resistor.
Rseries > Rtrace
Rout
Footprints must be laid out for optional EMI-reducing capac-
itors, which should be placed as close to the terminating
resistor as is physically possible. Typical values of these
capacitors range from 4.7 pF to 22 pF.
A Ferrite Bead
may
be used to isolate the Board V
from
the clock generator V
DD
island. Ensure that the Ferrite Bead
t
PR
T
PF
T
DC
Z
o
Rising Edge Propagation Delay
Falling Edge Propagation Delay
Duty Cycle
AC Output Impedance
3.0
3.0
50
5.0
5.0
60
ns
ns
%
Measured at 1.5V
AC Electrical Specifications
(continued)
Parameter
Description
Test Condition
Min.
Max.
Unit
0.1
μ
F
V
DD
CLK out
C
LOAD
OUTPUTS
GND
Figure 1. Test Circuit
SDRAM
SDATA
SCLK
BUF_IN
CPUCLK
PCICLK
USBCLK
REF
APIC
VDD
VSS
Ct
Rs
Rs
VDD 3.3V
Cd 0.1uF
This frequency synthesizer is used to generate
CPU, PCL,USB, REF and APIC Clocks
CY2281
SSOP 28
CY2310BNZ
SSOP 28
Cd = Decoupling Capacitor
Ct = Optional EMI-Reducing Capacitor
Rs = Series Terminating Resistors
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