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參數(shù)資料
| 型號： | CY2308ZC-1HT |
| 英文描述： | Eight Distributed-Output Clock Driver |
| 中文描述： | 八分布式輸出時鐘驅(qū)動器 |
| 文件頁數(shù)： | 2/9頁 |
| 文件大小： | 110K |
| 代理商： | CY2308ZC-1HT |
CY23020-3
Document #: 38-07473 Rev. *A
Page 2 of 9
Pin Definitions
[1]
Pin Name
REF+
REF-
Pin No.
39
40
Pin
Type
I
Pin Description
Reference Inputs
. Output signals are synchronized to the crossing point of REF+ and REF–
signals. In DC mode, the REF+/REF- inputs must be held at opposite logical states. For
optimal performance, the impedances seen by these two inputs must be equal.
Feedback Inputs
. Input FBIN+/FBIN- must be fed by one of the outputs to ensure proper
functionality. If the trace between FBIN+/FBIN- and FBOUT+/FBOUT- is equal in length to
the traces between the outputs and the signal destinations, then the signals received at the
destinations will be synchronized to the clock signal at REF+/REF- inputs. In DC mode,
FBIN+/FBIN- inputs must be held at opposite logical states. For best performance, the
impedances seen by these two inputs must be equal.
Feedback Output
.
In order to complete the phase locked loop, similar polarity outputs must
be connected back to the FBIN+ and FBIN- pins. Any
of the outputs may actually be used
as the feedback source.
Differential Q1 Outputs
. Refer to
Tables 1,2, and 3
for configuration.
Differential Q2 Outputs
. Refer to
Tables 1,2, and 3
for configuration.
Differential Q3 Outputs
. Refer to
Tables 1,2, and 3
for configuration.
Differential Q4 Outputs
. Refer to
Tables 1,2, and 3
for configuration.
Differential Q5 Outputs
. Refer to
Tables 1,2, and 3
for configuration.
Differential Q6 Outputs
. Refer to
Tables 1,2, and 3
for configuration.
Differential Q7 Outputs
. Refer to
Tables 1,2, and 3
for configuration.
Differential Q8 Outputs
. Refer to
Tables 1,2, and 3
for configuration.
Differential Q9 Outputs
.
Refer to
Tables 1,2, and 3
for configuration.
Frequency Range Selection Input
. To determine the correct connection for this pin, refer
to
Table 2
. This should be a static input
PLL Locked Output
. When this output is HIGH, the PLL in the CY23020-3 is in steady state
operation mode (Locked). When this signal is LOW, the PLL is in the process of locking onto
the reference signal.
Output/PLL Enable Selection Bits
. Refer to
Table 1
.
Analog Power Connection
. Connect to 3.3V.
Analog Ground Connection
. Connect to common system ground plane.
Output Buffer Power Connections
. Connect 3.3V
FBIN+
FBIN-
46
45
I
FBOUT+
FBOUT-
48
1
O
Q1+, Q1-
Q2+, Q2-
Q3+, Q3-
Q4 +, Q4-
Q5+, Q5-
Q6+, Q6-
Q7+, Q7-
Q8+, Q8-
Q9+, Q9-
RANGE
1
4, 3
6, 7
10, 9
12, 13
25, 24
27, 28
31, 30
33, 34
37, 36
18
O
O
O
O
O
O
O
O
O
I
LOCK
43
O
S1:2
VDDC
GNDC
VDD
16, 15
20, 21, 42
19, 22, 41
5, 11, 26, 32,
38, 47
2, 8, 14, 23,
29, 35
17
I
P
G
P
GND
G
Ground Connections
. Connect to common system ground plane.
MUL
[2]
I
Multiplication Factor Select
. When set HIGH, the outputs will run at twice the speed of the
reference signal. This should be a static input.
Do Not Connect
. This pin must be left floating. This pin is used by the factory for testing
purposes.
NC
44
NC
Table 1. Output Configuration
S1
0
0
1
1
S2
0
1
0
1
Outputs
PLL
Three-state
Reserved
Reference Input
PLL Output
Shutdown
Shutdown
Enabled
Notes:
1.
2.
There are no power-up sequence requirements on the power supply pins of the CY23020-3.
RANGE and MUL have a ~100k pull-down.
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