- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄223637 > CY2308SC-5H (CYPRESS SEMICONDUCTOR CORP) 3.3V Zero Delay Buffer PDF資料下載
參數(shù)資料
| 型號(hào)： | CY2308SC-5H |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 3.3V Zero Delay Buffer |
| 中文描述： | 2308 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封裝： | 0.150 INCH, MS-012, SOIC-16 |
| 文件頁(yè)數(shù)： | 8/14頁(yè) |
| 文件大?。?/td> | 238K |
| 代理商： | CY2308SC-5H |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)當(dāng)前第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)
CY2308
Document #: 38-07146 Rev. *D
Page 3 of 14
Zero Delay and Skew Control
To close the feedback loop of the CY2308, the FBK pin can be
driven from any of the eight available output pins. The output
driving the FBK pin will be driving a total load of 7 pF plus any
additional load that it drives. The relative loading of this output
(with respect to the remaining outputs) can adjust the
input-output delay. This is shown in the graph above.
For applications requiring zero input-output delay, all outputs
including the one providing feedback should be equally
loaded. If input-output delay adjustments are required, use the
above graph to calculate loading differences between the
feedback output and remaining outputs.
For zero output-output skew, be sure to load outputs equally.
For further information on using CY2308, refer to the appli-
cation note “CY2308: Zero Delay Buffer.”
Maximum Ratings
Supply Voltage to Ground Potential................–0.5V to +7.0V
DC Input Voltage (Except Ref) .............. –0.5V to VDD + 0.5V
DC Input Voltage REF ........................................... –0.5 to 7V
Storage Temperature.................................. –65°C to +150°C
Junction Temperature .................................................. 150°C
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ............................. >2000V
REF. Input to CLKA/CLKB Delay v/s Difference in Loading between FBK pin and CLKA/CLKB Pins
Operating Conditions for CY2308SC-XX Commercial Temperature Devices
Parameter
Description
Min.
Max.
Unit
VDD
Supply Voltage
3.0
3.6
V
TA
Operating Temperature (Ambient Temperature)
0
70
°C
CL
Load Capacitance, below 100 MHz
–
30
pF
Load Capacitance, from 100 MHz to 133 MHz
–
15
pF
CIN
Input Capacitance[6]
–7
pF
tPU
Power-up time for all VDDs to reach minimum specified voltage
(power ramps must be monotonic)
0.05
50
ms
Note:
6. Applies to both Ref Clock and FBK.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY2308SI-3 | 3.3V Zero Delay Buffer |
| CY2308SI-1H | 3.3V Zero Delay Buffer |
| CY2308SI-2 | 3.3V Zero Delay Buffer |
| CY2308SI-4 | 3.3V Zero Delay Buffer |
| CY2308 | 3.3V Zero Delay Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY2308SC-5HT | 制造商:Cypress Semiconductor 功能描述:Zero Delay PLL Clock Driver Single 10MHz to 133MHz 16-Pin SOIC T/R |
| CY2308SI-1 | 功能描述:IC CLK ZDB 8OUT 133MHZ 16SOIC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 產(chǎn)品變化通告:Product Discontinuation 04/May/2011 標(biāo)準(zhǔn)包裝:96 系列:- 類型:時(shí)鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無(wú)/無(wú) 頻率 - 最大:133.3MHz 除法器/乘法器:是/無(wú) 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| CY2308SI-1H | 功能描述:時(shí)鐘緩沖器 3.3VZDB COM RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| CY2308SI-1HT | 制造商:Cypress Semiconductor 功能描述:Zero Delay PLL Clock Driver Single 10MHz to 133MHz 16-Pin SOIC T/R |
| CY2308SI-1T | 制造商:Cypress Semiconductor 功能描述:Zero Delay PLL Clock Driver Single 10MHz to 133MHz 16-Pin SOIC T/R |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。