參數(shù)資料
型號： CY2308SC-3
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： 時鐘及定時
英文描述： 3.3V Zero Delay Buffer
中文描述： 2308 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
封裝： 0.150 INCH, MS-012, SOIC-16
文件頁數(shù)： 11/15頁
文件大小： 371K
代理商： CY2308SC-3
CY2308
Document Number: 38-07146 Rev. *H
Page 5 of 15
t3
Rise Time[7, 8]
(–1, –2, –3, –4)
Measured between 0.8V and 2.0V,
30 pF load
–
2.20
ns
t3
Rise Time[7, 8]
(–1, –2, –3, –4)
Measured between 0.8V and 2.0V,
15 pF load
–
1.50
ns
t3
Rise Time[7, 8]
(–1H, –5H)
Measured between 0.8V and 2.0V,
30 pF load
–
1.50
ns
t4
Fall Time[7, 8]
(–1, –2, –3, –4)
Measured between 0.8V and 2.0V,
30 pF load
–
2.20
ns
t4
Fall Time[7, 8]
(–1, –2, –3, –4)
Measured between 0.8V and 2.0V,
15 pF load
–
1.50
ns
t4
Fall Time[7, 8]
(–1H, –5H)
Measured between 0.8V and 2.0V,
30 pF load
–
1.25
ns
t5
Output to Output Skew on
same Bank
(–1, –2, –3, –4)[7, 8]
All outputs equally loaded
–
200
ps
Output to Output Skew (–1H,
–5H)
All outputs equally loaded
–
200
ps
Output Bank A to Output
Bank B Skew (–1, –4, –5H)
All outputs equally loaded
–
200
ps
Output Bank A to Output
Bank B Skew (–2, –3)
All outputs equally loaded
–
400
ps
t6
Delay, REF Rising Edge to
FBK Rising Edge[7, 8]
Measured at VDD/2
–
0
±250
ps
t7
Device to Device Skew[7, 8]
Measured at VDD/2 on the FBK pins
of devices
–
0
700
ps
t8
Output Slew Rate[7, 8]
Measured between 0.8V and 2.0V on
–1H, –5H device using Test Circuit 2
1–
V/ns
tJ
Cycle to Cycle Jitter[7, 8]
(–1, –1H, –4, –5H)
Measured at 66.67 MHz, loaded
outputs,
15 pF load
–
75
200
ps
Measured at 66.67 MHz, loaded
outputs,
30 pF load
–
200
ps
Measured at 133.3 MHz, loaded
outputs,
15 pF load
–
100
ps
tJ
Cycle to Cycle Jitter[7, 8]
(–2, –3)
Measured at 66.67 MHz, loaded
outputs
30 pF load
–
400
ps
Measured at 66.67 MHz, loaded
outputs
15 pF load
–
400
ps
tLOCK
PLL Lock Time[7, 8]
Stable power supply, valid clocks
presented on REF and FBK pins
––
1.0
ms
Switching Characteristics for Commercial Temperature Devices (continued)
Parameter[8]
Name
Test Conditions
Min
Typ.
Max
Unit
相關PDF資料
PDF描述
CY2308SC-4 3.3V Zero Delay Buffer
CY2308SI-1 3.3V Zero Delay Buffer
CY2308SC-5H 3.3V Zero Delay Buffer
CY2308SI-3 3.3V Zero Delay Buffer
CY2308SI-1H 3.3V Zero Delay Buffer
相關代理商/技術參數(shù)
參數(shù)描述
CY2308SC-3T 制造商:Cypress Semiconductor 功能描述:Zero Delay PLL Clock Driver Single 10MHz to 133MHz 16-Pin SOIC T/R 制造商:Rochester Electronics LLC 功能描述:3.3 V ZERO DELAY BUFFER - Bulk
CY2308SC-4 功能描述:時鐘緩沖器 3.3VZDB COM RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel
CY2308SC-4T 制造商:Cypress Semiconductor 功能描述:Zero Delay PLL Clock Driver Single 10MHz to 133MHz 16-Pin SOIC T/R
CY2308SC-5H 功能描述:IC CLK ZDB 8OUT 133MHZ 16SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應商設備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR
CY2308SC-5HT 制造商:Cypress Semiconductor 功能描述:Zero Delay PLL Clock Driver Single 10MHz to 133MHz 16-Pin SOIC T/R
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