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參數(shù)資料
| 型號： | CY2254 |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | Two-PLL Clock Generator(二鎖相環(huán)時鐘發(fā)生器) |
| 中文描述： | 66.66 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28 |
| 封裝： | 0.300 INCH, PLASTIC, SOIC-28 |
| 文件頁數(shù)： | 1/3頁 |
| 文件大?。?/td> | 54K |
| 代理商： | CY2254 |
fax id: 3611
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
May 9, 1995 - Revised July 3, 1997
408-943-2600
Understanding the CY2254
Introduction
The CY2254 is a two-PLL clock generator for the Intel Tri-
ton chipset-based motherboard and other Pentium moth-
erboards. It features four high-drive outputs at the CPU clock
frequency (50, 60, or 66.66 MHz, selected by two pins), six
high-drive synchronous PCI clock outputs at half the frequen-
cy of the CPU clocks, two high-drive Reference outputs at
14.318 MHz, a 12-MHz Keyboard clock output, and a 24-MHz
Floppy clock output. This application note discusses the in-
ternal architecture of the CY2254, and provides recommen-
dations for using it in a system.
CY2254 Features
The logic block diagram of the CY2254 is shown in Figure 1
The device accepts input from a 14.318-MHz parallel-reso-
nant crystal. This signal is then fed to the two internal PLLs,
which generate the required frequencies on the outputs. All
clock outputs are controlled by an active-HIGH Output Enable
pin, which three-states the outputs when deasserted. Table 1
shows the CY2254 function table.
CPU Clock Outputs
The CY2254 CPU PLL generates four outputs at the CPU
clock frequencies of 50, 60 or 66.66 MHz, by applying appro-
priate levels on the select inputs, S0 and S1. All CPU clock
outputs meet the Pentium’s maximum cycle-cycle jitter spec-
ification of 200 ps. Finally, all CPU clock outputs are
skew-controlled, with a maximum skew of 250 ps between
them.
PCI Clock Outputs
The CPU PLL output, after being internally divided by two,
drives six outputs at one-half the CPU clock frequency. In
addition, these PCI clock outputs lag the CPU clock outputs
by 1 to 5 ns. Finally, all PCI clocks outputs are skew-con-
trolled, with a maximum skew of 500 ps between them.
Figure 1. CY2254 Logic Block Diagram
XTALOUT
XTALIN
Ref0 (14.318 MHz)
14.318
MHz
Ref1 (14.318 MHz)
24 MHz (floppy disk)
12 MHz (keyboard)
PCLK0 (CPU clk 0)
PCLK1 (CPU clk 1)
PCLK2 (CPU clk 2)
PCLK3 (CPU clk 3)
BCLK0 (PCI clk 0)
÷
2
÷
2
2:1
2:1
SYS
PLL
÷
2
CPU
PLL
ROM
S0
S1
OE
÷
2
DELAY
BCLK1 (PCI clk 1)
BCLK2 (PCI clk 2)
BCLK3 (PCI clk 3)
BCLK4 (PCI clk 4)
BCLK5 (PCI clk 5)
Note:
PCLK = CPU Clock
BCLK = PCI Bus Clock
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY2254A | 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:Pentium㈢ Processor Compatible Clock Synthesizer/Driver |
| CY2254ASC-1 | 制造商:Rochester Electronics LLC 功能描述:PENTIUM COMPATIBLE CLOCK GENERATOR/DRIVER - Bulk |
| CY2254ASC-1T | 制造商:Cypress Semiconductor 功能描述:Pentium Processor Compatible 28-Pin SOIC T/R 制造商:Rochester Electronics LLC 功能描述:PENTIUM COMPATIBLE CLOCK GENERATOR/DRIVER - Tape and Reel |
| CY2254ASC-2 | 制造商:Cypress Semiconductor 功能描述:Pentium Processor Compatible 28-Pin SOIC |
| CY2255 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:CPU System Clock Generator |
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