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參數(shù)資料
| 型號(hào)： | CY22313 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時(shí)鐘和緩沖器 |
| 文件頁數(shù)： | 3/9頁 |
| 文件大?。?/td> | 79K |
| 代理商： | CY22313 |
CY22313
Document #: 38-07434 Rev. *D
Page 3 of 9
Absolute Maximum Conditions
(Above which the useful life may be impaired. For user guide-
lines; not tested.)
Supply Voltage...............................................–0.5V to +4.0V
DC Input Voltage ..............................–0.5V to + (V
DD
+ 0.5V)
Storage Temperature.................................. –65
°
C to +125
°
C
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ...............................2000V
Latch-up (per JEDEC 17).................................... > ±200 mA
Recommended Operating Conditions
[1]
Parameter
Description
Min.
3.15
Typ
3.45
Max.
3.6
Unit
V
V
DDRP
, V
DDVPA,
V
DDVP,
V
DDR
V
DD54
(2.5V)
V
DD54
(1.675V)
V
DDL
t
PU
Supply Voltage for PLL’s, Crystal Oscillator, and 3.45V Outputs
Supply Voltage for 2.5V Outputs
Supply Voltage for 1.675V Outputs
Supply Voltage for 1.8V Outputs
Power-up time for all V
DDS
to reach minimum specified voltage
(power ramps must be monotonic)
Operating Temperature, Ambient
Max. Load Capacitance, CMOS Output
External Reference Crystal
2.25
1.6
1.6
0.05
2.5
1.675
1.8
2.75
1.75
2.0
500
V
V
V
ms
T
A
C
LOAD_54MOUT
f
REF
0
+85
15
°
C
pF
MHz
18.432
Electrical Specifications
Parameter
I
OH[2]
Description
Conditions
Min.
8
6
5
8
6
5
Typ.
16
12
10
16
12
10
11
[4]
7
Max.
Unit
mA
mA
mA
mA
mA
mA
pF
pF
V
DD
V
DD
k
k
mA
Output High Current, 2.5V outputs
[3]
Output High Current, 1.8V outputs
[3]
Output High Current, 1.675V outputs
[3]
V
= V
DD
– 0.5, V
DD
= 1.675V
Output Low Current, 2.5V outputs
[3]
Output Low Current, 1.8V outputs
[3]
Output Low Current, 1.675V outputs
[3]
V
OL
= 0.5V, V
DD
= 1.675V
Crystal Load Capacitance
[3]
Input Pin Capacitance
[3]
HIGH-Level Input Voltage
LOW-Level Input Voltage
FS Input Resistor
S Input Resistor
Total Power Supply Current
V
OH
= V
DD
– 0.5, V
DD
= 2.5V
V
OH
= V
DD
– 0.5, V
DD
= 1.8V
I
OL[2]
V
OL
= 0.5V, V
DD
= 2.5V
V
OL
= 0.5V, V
DD
= 1.8V
C
XTAL
C
LOAD_IN
V
IH
V
IL
R
I_FS
R
I_S
I
DD
Total effective load of internal load caps
Except crystal pins
CMOS levels,% of V
DDRP
/V
DDVPA
/V
DDVP
CMOS levels,% of V
DDRP
/V
DDVPA
/V
DDVP
Pull-down resistor on FS
Pull-up resistor on S
Sum of all supply currents
70%
30%
225
100
125
60
10
150
Direct Rambus Electrical Specifications
[3]
Parameter
V
CM
V
X
V
COS
V
COH
V
COL
r
OUT
Notes:
1.
Unless otherwise noted, Electrical and Switching Characteristics are guaranteed across these operating conditions.
2.
LCLK and 54MOUT outputs only.
3.
Guaranteed by design, not 100% tested.
4.
Identical Crystal Load Capacitance as CY2212ZC-2. Use the same crystal and X
IN
/ X
OUT
board layout as implemented with the original crystal-driven
CY2212ZC-2.
5.
Differential output crossing point voltages shown in
Figure 1.
6.
V
COS
= V
OH
– V
OL
.
7.
r
OUT
=
V
O
/
I
O
. This is defined at the output pins, not at the measurement point of
Figure 9
.
Description
Min.
1.35
1.25
0.4
Typ.
Max.
1.75
1.85
0.7
2.1
Unit
V
V
V
V
V
Differential output common-mode voltage
Differential output crossing-point voltage
[5]
Output Voltage swing (p-p single-ended)
[6]
Output high voltage
Output low voltage
Output dynamic resistance (at pins)
[7]
1.0
12
50
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