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參數(shù)資料
| 型號(hào)： | CY2081WAF |
| 英文描述： | MISCELLANEOUS CLOCK GENERATOR|DIE |
| 中文描述： | 雜項(xiàng)時(shí)鐘發(fā)生器|模具 |
| 文件頁(yè)數(shù)： | 3/6頁(yè) |
| 文件大小： | 73K |
| 代理商： | CY2081WAF |
CY2081A
3
Switching Characteristics
[8]
Parameter
Name
Description
Min.
Typ.
Max.
Unit
t
1
Output Period
Clock output range, 5V operation
10
[100 MHz]
2000
[500 KHz]
ns
t
1
Output Period
Clock output range, 3.3V operation
12.5
[80 MHz]
2000
[500 KHz]
ns
t
1A
Clock Jitter
[9]
Peak-to-peak period jitter, % of clock period
(f
OUT
≤
4 MHz)
Peak-to-peak period jitter
(4 MHz
≤
f
OUT
≤
16 MHz)
Peak-to-peak period jitter
(16 MHz
<
f
OUT
≤
50 MHz)
Peak-to-peak period jitter
(f
OUT
>
50 MHz)
Duty cycle for outputs, defined as t
2
÷
t
1[11]
f
OUT
> 66.67 MHz
Duty cycle for outputs, defined as t
2
÷
t
1[11]
f
OUT
≤
66.67 MHz
Output clock rise time
[12]
at C
L
=25 pF (15 pF
at 3.3V operation)
Output clock fall time
[12]
at C
L
=25 pF (15 pF
at 3.3V operation)
<0.5
1
%
t
1B
Clock Jitter
[9]
<0.7
1
ns
t
1C
Clock Jitter
[9]
<400
500
ps
t
1D
Clock Jitter
[9]
<250
350
ps
Output Duty Cycle
[10]
40%
50%
60%
45%
50%
55%
t
3
Rise time
3
5
ns
t
4
Fall time
2.5
4
ns
t
5
Frequency Slew Rate
Rate of change of frequency of CLKA
1
5
40
MHz/
ms
t
6
Power Up Stabiliza-
tion Time
Output clock stable time after power up
< 25
50
ms
Switching Waveforms
Notes:
8.
9.
Guaranteed by design, not 100% tested.
Jitter varies with configuration. All standard configurations sample tested at the factory conform to this limit. For more information on jitter, please refer to
the application note:
“
Jitter in PLL-Based Systems.
”
10. Reference Output duty cycle depends on XTALIN duty cycle.
11. Measured at 1.4V.
12. Measured between 0.4V and 2.4V.
All Outputs Duty Cycle and Rise/Fall Time
2081
–
3
OUTPUT
t
3
t
4
t
2
t
1
2.4V
0.4V
0.4V
2.4V
3.3V
0V
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